ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 43

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL50010
Data Sheet
2.11.9
Phase Lock Time
The Phase Lock Time is the time it takes a synchronizer to phase lock to the input signal. Phase lock occurs when
the input and the output signals are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) PLL loop filter
iv) PLL limiter
Although a short phase lock time is desirable, it is not always achievable due to other synchronizer requirements.
For instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases lock
time; and better (smaller) phase slope performance (limiter) will increase lock time.
The DPLL loop filter and limiter have been optimized to meet the Telcordia GR-1244-CORE jitter transfer and
phase alignment speed requirements. If the frequency of the DPLL internal feedback signal is -50 ppm and the
frequency of the input reference is +50 ppm, then the phase lock time is typically 15 seconds. However, in a device
power up situation, phase lock time can be up to 50 seconds. The phase lock time meets Telcordia GR-1244-CORE
Stratum 4E requirements.
2.12
Alignment Between Input and Output Frame Pulses
When the device is in DPLL Master mode, and CKi/FPi is the selected input reference and has no jitter, then the
ST-BUS output frame pulses align very closely to the ST-BUS input frame pulse. See Figure 40 on page 75 for
details. (The alignment shown is for when all bits in the DPOA register are 0.) If the CKi/FPi reference has jitter, the
output frame pulses will still align to the input frame pulse but the offset value is a function of the input jitter.
When the device is in DPLL Master mode, and the selected input reference is not CKi/FPi, then the output frame
pulses have no relationship with respect to the input frame pulse. In this case, the device’s output frame pulse(s)
must be used as the frame pulse(s) for the system, which means that the output frame pulse(s) will be supplied as
the input frame pulse to all devices, including the device itself.
When the device is in DPLL Bypass Mode, the output frame pulses align closely to the input frame pulse. See
Figure 40 for details.
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Zarlink Semiconductor Inc.