ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 10

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description
10, 23, 33,
43, 48, 58,
68, 78, 92,
32, 38, 47,
57, 67, 77,
LQFP Pin
127, 136,
9, 18, 21,
135, 145,
102, 113,
112, 126,
Number
146, 156
91, 101,
155
11
3
4
5
6
7
8
G5, G6, G7, G8
H5, H6, H7, H8
E5, E6, E7, E8
F5, F6, F7, F8
LBGA Ball
D5, D6, D7
J6, J7, J8
Number
F4, F9
D4, D9
B12
A12
B10
A10
B11
A11
G4
H4
E9
B9
J4
V
ss
Name
TRST
TMS
TCK
SG1
V
TDi
FPi
CKi
(GND)
DD
Zarlink Semiconductor Inc.
Power Supply for the device: +3.3 V
Ground.
Test Mode Select (3.3 V Tolerant Input with internal pull-
up): JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up resistor
when it is not driven.
Test Clock (5 V Tolerant Input): Provides the clock to the
JTAG test logic.
Test Reset (3.3 V Tolerant Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by putting it
in the Test-Logic-Reset state. This pin should be pulsed low
during power-up to ensure that the device is in the normal
functional mode. When JTAG is not being used, this pin should
be pulled low during normal operation.
Test Serial Data In (3.3 V Tolerant Input with internal pull-
up): JTAG serial test instructions and data are shifted in on this
pin. This pin is pulled high by an internal pull-up resistor when it
is not driven.
ST-BUS Frame Pulse Input (5 V Tolerant Input): This pin
accepts the frame pulse which stays low for 61 ns, 122 ns or
244 ns at the frame boundary. The frame pulse associating
with the highest input data rate has to be applied to this pin.
The frame pulse frequency is 8 kHz. The device also accepts
positive frame pulse if the FPINP bit is high in the Internal
Mode Selection register.
ST-BUS Clock Input (5 V Tolerant Input): This pin accepts an
4.096 MHz, 8.192 MHz or 16.384 MHz clock. The input clock
frequency has to be equal to or greater than twice of the
highest input data rate. The clock falling edge defines the input
frame boundary. The device also allows the clock rising edge to
define the frame boundary by programming the CKINP bit in
the Internal Mode Selection register.
APLL Test Control (3.3 V Input with internal pull-down): For
normal operation, this input MUST be low.
ZL50010
10
Description
Data Sheet