ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 31

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.8
The device supports the non-multiplexed microprocessor. The microprocessor port consists of a 16 bit parallel data
bus (D0 to 15), a 12 bit address bus (A0 to 11) and four control signals (CS, DS, R/W and DTA). The parallel
microprocessor port provides fast access to the internal registers, the connection and the data memories.
The connection memory locations can be read or written via the 16 bit microprocessor port. On the other hand, the
data memory locations can only be read (but not written) from the microprocessor port.
For the connection memory write operation, D0 to 11 of the data bus will be used and D12 to 15 are ignored (D12 to
15 should be driven low). For the connection memory read operation, D0 to D11 will be used and D12 to D15 will
output zeros. For the data memory read operation, D0 to D7 will be used and D8 to D15 will output zeros.
See Table on page 68 for the address mapping of the data memory. Refer to Figure 48 on page 82 for the
microprocessor port timing.
2.9
The DPLL meets the requirements of Telcordia GR-1244-CORE Stratum 4 enhanced specifications (Stratum 4E). It
can be set into one of three operating modes: Master, Freerun or Bypass.
The input streams STi0-15 are always sampled with the ST-BUS input clock CKi. The ST-BUS input frame pulse
FPi denotes the input frame boundary. The objective of the DPLL is to generate the high speed internal clock
MCKTDM (see Figure 25 on page 35). MCKTDM provides timing for the TDM switching function and timing for the
ST-BUS outputs. (In this context CKo0-2, FPo0-2, STo0-15 and STOHZ0-15 are collectively known as the ST-BUS
outputs.)
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Table 14 shows the three operating modes of the DPLL. The DPLL is controlled by the DOM (DPLL Operation
Mode) register and bit 14 of the Control Register (CR). The DPLL’s status is reported in the DPLL House Keeping
Register (DHKR). The DPOA (DPLL Output Adjustment) register advances or delays the ST-BUS outputs with
respect to the reference. These registers are described in Table 17 on page 50 for CR, Table 22 on page 55 for
DOM, Table 23 on page 57 for DOA, and Table 24 on page 57 for DHKR.
In Master mode, the DPLL synchronizes to one of the timing reference inputs to generate the internal clock
MCKTDM. Typically the timing references are from the network. The DPLL provides functions such as
automatic bit-error-free reference switching, jitter attenuation and holdover. The Master mode ST-BUS
output clocks and frame pulses are synchronized to the network reference and can be used as a system’s
ST-BUS timing source.
In Freerun mode, the DPLL is not synchronized to any of the timing references. It synthesizes the internal
clock MCKTDM based on the oscillator clock. Typically Freerun mode is used when a system’s timing is
independent of the network. In that case, the Freerun mode ST-BUS output clocks and frame pulses must be
used as the system’s ST-BUS timing source.
In Bypass mode, the DPLL is completely bypassed. The Analog Phase-Locked Loop (APLL) synchronizes to
the ST-BUS input clock CKi to generate the internal clock MCKTDM. Bypass mode is used when the
system’s ST-BUS timing is supplied by another device, e.g. another ZL50010 in Master mode.
Microprocessor Port
Digital Phase-Locked Loop (DPLL) Operation
STIN#QEN3
1
0
Table 13 - Quadrant Frame 3 LSB Replacement
Replace LSB of every channel in Quadrant 3 with "1"
No bit replacement occurs in Quadrant 3
Zarlink Semiconductor Inc.
ZL50010
31
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Data Sheet