ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 55

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

15 - 12
10 - 9
6 - 5
External Read/Write Address: 030
Bit
Reset Value: 0000
15
11
0
8
7
14
0
FS1 - FS0
FDM1 - 0
Unused
MRST
Name
SINV
PINV
13
0
H
12
0
Reserved. In normal functional mode, these bits MUST be set to zero.
MTIE Reset Bit: When MRST is low, the DPLL MTIE circuit is functional. When MRST
is high, the MTIE circuit will be reset - the DPLL output will align with the nearest edge
of the selected reference. (Note: After the realignment, the phase offset between the
input reference and DPLL output is the amount programmed into the DPOA register.)
Failure Detect Mode Bits: These two bits are used to choose among one of three
Failure Detection modes.
SEC_REF Input Inversion: When this bit is low, the SEC_REF input will not be
inverted. When this bit is high, the SEC_REF input will be inverted.
PRI_REF Input Inversion: When this bit is low, the PRI_REF input will not be
inverted. When this bit is high, the PRI_REF input will be inverted.
SEC_REF Frequency Selection Bits: These bits are used to specify the nominal
clock frequency of the SEC_REF input.
MRST
Table 22 - DPLL Operation Mode (DOM) Register Bits
11
FDM1
H
0
0
1
1
FDM1
10
FDM0
0
1
0
1
FDM0
FS1
9
0
0
1
1
Zarlink Semiconductor Inc.
Autodetect - Automatic Reference Re-arrangement based on
reference monitor results and choice of preferred reference
Reserved
Forced Primary - The DPLL is forced to use primary reference
only
Forced Secondary - The DPLL is forced to use secondary
reference only
SINV
ZL50010
8
FS0
0
1
0
1
55
PINV
7
Description
FS1
6
Secondary Reference
Failure Detection Mode
1.544 MHz
2.048 MHz
FS0
Reserved
5
8 kHz
FP1
4
FP0
3
REF
SEL
2
P_REF
SEL
1
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