ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 33

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.9.1.2
The DPLL monitors both the primary and secondary reference. When the reference the DPLL is currently
synchronized to becomes invalid, the DPLL’s response depends on which one of the failure detect modes has been
chosen: autodetect, forced primary or forced secondary. One of these failure detect modes must be chosen via the
FDM1-0 bits of the DOM register. After a device reset via the RESET pin, the autodetect mode is selected.
In autodetect mode (automatic reference switching), if both references are valid, the DPLL will synchronize to the
preferred reference. If the preferred reference becomes unreliable, the DPLL continues driving its output clock in a
stable holdover state until it makes a switch to the backup reference. If the preferred reference recovers, the DPLL
makes a switch back to the preferred reference. If necessary, the switch back can be prevented by changing the
preferred reference using the REFSEL bit in the DOM register after the switch to the backup reference has
occurred.
If both references are unreliable, the DPLL will drive its output clock using stable holdover values until one of the
references becomes valid. If CKi/FPi is selected as the preferred reference, the user must ensure that the FPi and
CKi input signals are re-applied after the CKi/FPi reference is lost (or failed). When the CKi/FPi reference is lost,
since FPi and CKi are used to sample the input data streams STi0-15, the TDM switching from STi to STo will not
work.
In forced primary mode, the DPLL will synchronize to the primary reference only. The DPLL will not switch to the
secondary reference under any circumstance including the loss of the primary reference. If the primary reference
failed, the DPLL will not go into holdover mode and synchronization will be lost. Similarly in forced secondary mode
the DPLL will synchronize to the secondary reference only and will not switch to the primary reference or go into
holdover under any circumstance. The choice of preferred reference has no effect in these forced modes.
When a conventional PLL is locked to its reference, there is no phase difference between the input reference and
the PLL output. For the DPLL, the input references can have any phase relationship between them. During a
reference switch, if the DPLL output follows the phase of the new reference, a large phase jump could occur. The
phase jump would be transferred to the ST-BUS outputs. The DPLL’s MTIE (Maximum Time Interval Error) feature
preserves the continuity of the DPLL output so that it appears no reference switch had occurred. The MTIE circuit is
not perfect however, and a small Time Interval Error is still incurred per reference switch. To align the DPLL output
clock to the nearest edge of the selected input reference, the MTIE reset bit (MRST bit in the DOM register) can be
used.
Unlike some designs, switching between references which are at different nominal frequencies do not require
intervention such as device reset.
2.9.1.3
Reference switching is managed by the state machine shown in Figure 27 on page 37. The state machine can be in
one of six states corresponding to the names and numbers in the bubbles in Figure 27. The state number is
reported in the ST2-0 bits of the DHKR register. The validity of the primary and secondary references are reported
in the PFD and SFD bits of the DHKR register respectively.
2.9.1.4
The ST-BUS outputs (CKo0-2, FPo0-2, STo0-15 and STOHZ0-15) can be shifted to lead (advancement) or lag
(delay) the reference. The DPOA register provides this adjustment. Coarse lead or lag adjustment is programmed
via the POS6-0 bits, while fine delay (lag) control is via the SKC2-0 bits.
Master Mode Reference Switching
DPLL Status Reporting
Master Mode Output Offset Adjustment
Zarlink Semiconductor Inc.
ZL50010
33
Data Sheet