UPD17073 NEC, UPD17073 Datasheet - Page 199

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

20.6 Power Failure Detection
effected by application of supply voltage V
these are initialized by detecting a power failure.
20.6.1 Power Failure Detector Circuit
disable flip-flop that is reset by the output (power-ON clear signal) of the voltage detector circuit, and basic timer 0
carry.
reads the BTM0CY flag has been executed.
cleared, and setting of the BTM0CY flag is inhibited until an instruction that reads the BTM0CY flag is executed later.
timer 0 carry FF setting pulse rises. Therefore, whether power-ON reset (power failure) or CE reset (not power failure)
has been effected can be judged by checking the content of the BTM0CY flag, when the device has been reset. That
is, if the BTM0CY flag is cleared to 0, power-ON reset has been effected; if the flag is set to 1, CE reset has been
effected.
20-8 and the operation of the BTM0CY flag.
The power failure detection feature is used to judge, when the device has been reset, whether the reset has been
Because the contents of the data memory and output ports are “undefined” on power application, the contents of
The power failure can be detected by detecting the BTM0CY flag by using a power failure detector circuit.
The power failure detector circuit consists of a voltage detector circuit as shown in Figure 20-1, basic timer 0 carry
The basic timer 0 carry disable FF is set to 1 by the power-ON clear signal, and reset to 0 when an instruction that
While the basic timer 0 carry disable FF is set to 1, the BTM0CY flag is not set to 1.
If the power-ON clear signal is output (at power-ON reset), therefore, the program is started with the BTM0CY flag
Once the instruction that reads the BTM0CY flag has been executed, the BTM0CY flag is set each time the basic
The voltage at which a power failure can be detected is the same voltage at which power-ON reset is effected.
Figure 20-8 illustrates the status transition of the BTM0CY flag. Figure 20-9 shows the timing chart of Figure
Figure 20-7. Power Failure Detection Flowchart
Not power failure
DD
or by the CE pin.
Program starts
Power failure
detected
Power failure
Initializes data
memory and
output ports
PD17072,17073
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