UPD17073 NEC, UPD17073 Datasheet - Page 190

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

20.3 CE Reset
timer 0 carry FF setting pulse, and the device is reset.
register is initialized to an initial value by the RESET signal, and the program is executed from address 0000H.
whether the clock stop mode is used or not.
20.3.1 CE reset when clock stop mode (STOP s instruction) is not used
RESET signal is output at the rising edge of the basic timer 0 carry FF setting pulse selected at that time (t
ms), and reset is effected.
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The CE reset is effected by making the CE pin high.
When the CE pin goes high, the RESET signal is output in synchronization with the rising edge of the next basic
When the CE reset has been effected, part of the program counter, stack, system register, and peripheral control
For the initial value, refer to the description of each register.The operation of the CE reset differs depending on
This is described in 20.3.1 and 20.3.2.
20.3.3 describes the points to be noted when effecting the CE reset.
Figure 20-2 shows the operation.
When the clock stop mode (STOP s instruction) is not used, and after the CE pin has gone high, therefore, the
Reset
signals
Basic timer 0 carry
FF setting pulse
V
CE
X
IRES
RES
RESET
DD
OUT
Figure 20-2. CE Reset Operation When Clock Stop Mode Is Not Used
5 V
0 V
H
L
H
L
H
L
H
L
H
L
H
L
Normal operation
If basic timer 0 carry FF setting time t
0 < t < 125 ms during this period because of the rising timing of the CE pin.
During this period, the program continues operation.
operation
Normal
CE reset is effected at rising edge of basic
timer 0 carry FF setting pulse.
SET
= 125 ms,
PD17072,17073
SET
= 125