UPD17073 NEC, UPD17073 Datasheet - Page 143
UPD17073
Manufacturer Part Number
UPD17073
Description
4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
Manufacturer
NEC
Datasheet
1.UPD17073.pdf
(226 pages)
- Current page: 143 of 226
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15.7 Status on Reset
15.7.1 On power-ON reset
15.7.2 On clock stop
15.7.3 On CE reset
15.7.4 In halt status
(1) Transition from clock stop to CE reset status
(2) On CE reset
The PLL mode select register is initialized to 0000B; therefore, the PLL disable status is set.
The PLL disable status is set when the CE pin goes low.
The set status is retained if the CE pin is high.
The PLL mode select register has been initialized to 0000B when the clock stop instruction has been executed;
therefore, the PLL disable status is set.
The PLL reference frequency select register retains the previous status; therefore, the previous status is
restored when the CE pin goes high.
PD17072,17073
143
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