UPD17073 NEC, UPD17073 Datasheet - Page 170

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

19.2 Halt Function
19.2.1 General
released. Therefore, the current consumption of the device is reduced by the operating current of the CPU in the halt
status.
19.2.2 Halt status
by the “HALT h” instruction. However, the peripheral hardware retains the status set before the HALT h instruction
is executed.
19.2.3 Halt release condition
instruction.
has been satisfied.
appropriate reset operation is performed.
when the device is reset (power-ON reset or CE reset).
170
The halt function is to stop the operation clock of the CPU by executing the “HALT h” instruction.
When this instruction has been executed, the program is stopped and is not executed unless the halt status is
The halt status is released by key input, basic timer 0, or interrupt.
The releasing condition is specified by the operand “h” of the HALT h instruction.
The HALT h instruction is valid regardless of the input level of the CE pin.
In the halt status, all the operations of the CPU are stopped. In other words, the program execution is stopped
For the operation of each peripheral hardware, refer to 19.4 Device Operations in Halt and Clock Stop Statuses.
Figure 19-2 shows the halt release conditions.
The halt release condition is set by 4-bit data that is specified by the operand “h” of the HALT h instruction.
The halt status is released when the condition specified as “1” in operand “h” is satisfied.
When the halt status has been released, program execution is started from the instruction next to "HALT h"
If two or more release conditions are specified, the halt status is released if any one of the specified conditions
When the device has been reset (by means of power-ON reset or CE reset), the halt status is released, and the
If 0000B is set as the halt release condition “h”, no release condition is set. In this case, the halt status is released
b
HALT h (4 bits)
3
Operand
b
2
b
1
b
0
Releases if high level is input to port 1A
Releases if basic timer 0 carry FF is set (1)
Undefined (Fix this bit to "0".)
Releases when interrupt request flag and interrupt enable flag are set
(When executing EI and DI instructions)
0: Does not release halt status even if condition is satisfied
1: Releases halt status if condition is satisfied
Figure 19-2. Halt Release Condition
Sets halt status release condition
PD17072,17073