UPD17073 NEC, UPD17073 Datasheet

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UPD17073

Manufacturer Part Number
UPD17073
Description
4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
Manufacturer
NEC
Datasheet

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UPD17073GB-572-1A7-A
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Document No. U11450EJ1V0DS00 (1st edition)
Date Published September 1996 P
Printed in Japan
DESCRIPTION
organizing a digital tuning system.
and control peripheral hardware with a single instruction. All the instructions are 16-bit one-word instructions.
synthesizer, and an intermediate frequency (IF) counter are integrated in addition to I/O ports, an LCD controller/driver,
A/D converter, and BEEP.
battery-cell driven portable devices such as portable radio equipment, headphone stereos, or radio cassette
recorders.
FEATURES
• 17K architecture: general-purpose register system
• Program memory (ROM)
• General-purpose data memory (RAM)
• Instruction execution time
• Decimal operation
• Table reference
• Hardware for PLL frequency synthesizer
• Various peripheral hardware
• Many interrupts
• Power-ON reset, CE reset, and power failure detector
• CMOS low power consumption
• Supply voltage: V
PD17072 or 17073.
Dual modulus prescaler (230 MHz max.), programmable divider, phase comparator, charge pump
General-purpose I/O ports, LCD controller/driver, serial interface, A/D converter, BEEP, intermediate frequency
(IF) counter
The CPU employs 17K architecture and can manipulate the data memory directly, perform arithmetic operations,
As peripheral hardware, a prescaler that can operate at up to 230 MHz for a digital tuning system, a PLL frequency
Therefore, a high-performance, multi-function digital tuning system can be configured with a single chip of
Because the PD17072 and 17073 can operate at low voltage (V
PD17072 and 17073 are low-voltage 4-bit single-chip CMOS microcontrollers containing hardware ideal for
Unless otherwise stated, the PD17073 is taken as a representative product in this document.
6 KB (3072
8 KB (4096
176
53.3 s (with 75-kHz crystal resonator: normal operation)
106.6 s (with 75-kHz crystal resonator: low-speed mode)
External: 1 channel
Internal: 2 channels
4 bits
WITH HARDWARE FOR DIGITAL TUNING SYSTEM
DD
16 bits):
16 bits):
= 1.8 to 3.6 V
4-BIT SINGLE-CHIP MICROCONTROLLER
The information in this document is subject to change without notice.
PD17072
PD17073
DATA SHEET
PD17072,17073
MOS INTEGRATED CIRCUIT
DD
= 1.8 to 3.6 V), they are ideal for controlling
©
1996

Related parts for UPD17073

UPD17073 Summary of contents

Page 1

SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM DESCRIPTION PD17072 and 17073 are low-voltage 4-bit single-chip CMOS microcontrollers containing hardware ideal for organizing a digital tuning system. The CPU employs 17K architecture and can manipulate the data memory directly, ...

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ORDERING INFORMATION Part Number PD17072GB- -1A7 PD17072GB- -9EU PD17073GB- -1A7 PD17073GB- -9EU Remark is a ROM code number. 2 Package 56-pin plastic QFP (10 10 mm, 0.65-mm pitch) 64-pin plastic TQFP (fine pitch) (10 10 mm, 0.5-mm pitch) 56-pin plastic ...

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FUNCTION OUTLINE Item Program memory (ROM) • 6K bytes (3072 • 8K bytes (4096 • Table reference area: 4096 General-purpose data memory • 176 (RAM) General-purpose register: 16 (fixed at 00H through 0FH of BANK0, shared with data buffers.) LCD ...

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BLOCK DIAGRAM P0A0-P0A3 P0B0-P0B3 P0C0, P0C1 Port P0D2, P0D3 P1A0-P1A3 P1B0-P1B3 P1C0 REG 0 LCD REG 1 LCD Voltage Doubler CAP 0 LCD CAP 1 LCD COM0 LCD COM3 Controller LCD0 /Driver LCD14 X CPU IN OSC X Peripheral OUT ...

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PIN CONFIGURATION (Top View) 56-pin plastic QFP (10 10 mm) PD17072GB- -1A7 PD17073GB- -1A7 P1C0/SO0 1 P0A0 2 P0A1 3 P0A2 4 P0A3 5 P1B0 6 ...

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TQFP (fine pitch) (10 PD17072GB- -9EU PD17073GB- -9EU P1C0/SO0 1 P0A0 2 P0A1 3 P0A2 P0A3 6 P1B0 7 ...

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... PIN IDENTIFICATION AD0, AD1 : A/D converter input AMIFC : Intermediate frequency (IF) counter input BEEP : BEEP output CAP 0, CAP 1 : Capacitor connection for LCD drive voltage CLD LCD CE : Chip enable COM0-COM2 : LCD common signal output EO : Error out FMIFC : Intermediate frequency (IF) counter input GND : Ground INT ...

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PIN FUNCTION .................................................................................................................................. 12 1.1 Pin Function List ...................................................................................................................................... 12 1.2 Equivalent Circuits of Pins ....................................................................................................................... 15 1.3 Processing of Unused Pins ..................................................................................................................... 18 1.4 Notes on Using CE Pin ............................................................................................................................ 19 2. PROGRAM MEMORY (ROM) ........................................................................................................... 20 2.1 ...

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PERIPHERAL CONTROL REGISTERS ........................................................................................... 45 8.1 Outline of Peripheral Control Registers .................................................................................................. 45 8.2 Configuration and Function of Peripheral Control Registers ................................................................. 46 9. DATA BUFFER (DBF) ....................................................................................................................... 54 9.1 General ..................................................................................................................................................... 54 9.2 Data Buffer ............................................................................................................................................... 55 9.3 ...

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Presettable Shift Register ...................................................................................................................... 117 14.6 Wait Control Block ................................................................................................................................. 117 14.7 Serial Interface Operation ..................................................................................................................... 118 14.8 Notes on Setting and Reading Data ..................................................................................................... 122 14.9 Operational Outline of Serial Interface ................................................................................................. 123 14.10 Status on Reset ..................................................................................................................................... ...

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... System Register (SYSREG) .................................................................................................................. 208 22.3 LCD Segment Register .......................................................................................................................... 209 22.4 Port Register .......................................................................................................................................... 210 22.5 Peripheral Control Register ................................................................................................................... 211 22.6 Peripheral Hardware Register ..................................................................................................................... 22.7 Others ..................................................................................................................................................... 213 23. ELECTRICAL CHARACTERISTICS ............................................................................................... 214 24. PACKAGE DRAWINGS ................................................................................................................... 217 25. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 219 APPENDIX A. NOTES ON CONNECTING CRYSTAL RESONATOR ................................................ 220 APPENDIX B. DEVELOPMENT TOOLS.............................................................................................. 221 PD17072,17073 11 ...

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... Output from charge pump of PLL frequency synthesizer 20 23 VCOL Input local oscillation frequency of PLL VCOH 22 25 REG0 Output of PLL voltage regulator. Connect this pin to GND via 0.1- F capacitor. 12 Function Output format CMOS push-pull CMOS push-pull CMOS push-pull — CMOS push-pull CMOS push-pull — CMOS 3-state — ...

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... Pins for connecting crystal resonator for system OUT clock oscillation REG1 Output of voltage regulator for oscillation circuit. Connect this pin to GND via 0.1- F capacitor. • REG 0 REG 1, REG LCD LCD 28 32 CAP 0 LCD drive power pins. ...

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... P0B3/SI/SO1 • Can be set in input or output mode in 1-bit units. • SCK • Serial clock I/O • SO1 • Serial data output • SI • Serial data input — connection Function Output format CMOS ternary output CMOS push-pull — — ...

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Equivalent Circuits of Pins (1) P0B (P0B3/SI/SO1, P0B2/SCK, P0B1, P0B0) P0C (P0C1, P0C0) P0D (P0D3/FMIFC/AMIFC, P0D2/AMIFC) (2) P0A (P0A3, P0A2, P0A1, P0A0) P1B (P1B3, P1B2, P1B1, P1B0) P1C (P1C0/SO0) LCD14-LCD0 BEEP EO (3) P1A (P1A3/AD1, P1A2/AD0, P1A1, P1A0) (Input) ...

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CE (Schmitt trigger input) (5) INT (Schmitt trigger input) (6) X (output), X (input) OUT High ON resistance X OUT flag V DD High resistance V DD PD17072,17073 ...

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COM3 through COM0 (output) (8) VCOH (input) (9) VCOL (input) PLL disable signal PLL disable signal V V LCD0 LCD1 High ON resistance High ON resistance V DD High ON resistance V DD PD17072,17073 17 ...

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... Connect each of these pins to V Open Open Connect to V via resistor DD Open Connect to GND via resistor Open Connect each of these pins to GND via resistor via resistor) or pulling down (connecting to GND via resistor) a pin DD PD17072,17073 Note 2 or GND via resistor . DD Note 2 . Note 2 ...

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... Therefore, wire the CE pin with as short a wiring length as possible to suppress noise. If noise cannot be avoided, use external components as shown below to suppress noise. • Connect a diode with low V between CE and V F Diode with V DD low • Connect a capacitor between CE and PD17072,17073 ...

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PROGRAM MEMORY (ROM) 2.1 General Figure 2-1 shows the configuration of the program memory. As shown in this figure, the program memory consists of a program memory and a program counter. The addresses of the program memory are specified ...

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Program Memory Figure 2-2 shows the configuration of the program memory. As shown in this figure, the program memory is configured as follows: PD17072: 3072 16 bits (0000H-0BFFH) PD17073: 4096 16 bits (0000H-0FFFH) Therefore, the addresses of the program ...

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Execution Flow of Program Memory Execution of the program is controlled by the program counter which specifies an address of the program memory. Figure 2-4 shows the values to be set to the program counter when each instruction is ...

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ADDRESS STACK (ASK) 3.1 General Figure 3-1 outlines the address stack. The address stack consists of a stack pointer and an address stack register. The address of the address stack register is specified by the stack pointer. The address ...

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Stack Pointer (SP) Figure 3-3 shows the configuration and functions of the stack pointer. The stack pointer is a 4-bit binary counter. The stack pointer specifies the addresses of the address stack registers. The value of the stack pointer ...

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Operations of Address Stack 3.4.1 Subroutine call (“CALL addr” or “CALL @AR”) and return (“RET” or “RETSK”) instructions When a subroutine call instruction is executed, the value of the stack pointer is decremented by one and the return address ...

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DATA MEMORY (RAM) 4.1 General Figure 4-1 outlines the data memory. As shown in this figure, the data memory consists of a general-purpose data memory, system register, data buffer, general register, LCD segment register, port register, and peripheral control ...

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Configuration and Function of Data Memory Figure 4-2 shows the configuration of the data memory. As shown in this figure, the data memory is divided into three banks, and each bank consists of 128 nibbles with 7H row addresses ...

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General-purpose data memory The general-purpose data memory is allocated to the area of the data memory excluding the system register, LCD segment register, port register, and peripheral control register. With the PD17073, a total of 176 nibbles (176 be ...

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Figure 4-2. Configuration of Data Memory Column address Data memory BANK0 6 BANK1 ...

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Table 4-1. Data Memory Manipulation Instructions Operation Compare Transfer Judge 4.3 Addressing Data Memory Figure 4-3 shows how to address the data memory. An address of the data memory is specified by using a bank, row address, and column address. ...

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... Notes on Using Data Memory 4.4.1 On power-ON reset On power-ON reset, the contents of the general-purpose data memory are “undefined”. Initialize the memory if necessary. 4.4.2 Notes on data memory not provided If a data memory manipulation instruction is executed to manipulate an address where no data memory is assigned, the following operations are performed: (1) Device operation When a read instruction is executed, “ ...

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SYSTEM REGISTER (SYSREG) 5.1 General Figure 5-1 shows the location of the system register on the data memory and outline. As shown, the system register is assigned to addresses 74H-7FH of the data memory, regardless of bank. In other ...

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Address Register (AR) 5.2.1 Configuration of address register Figure 5-2 shows the configuration of the address register. As shown in this figure, the address register consists of 16 bits of the system register: 74H through 77H (AR3 through AR0). ...

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Functions of address register The address register specifies a program memory address when the table reference instruction (“MOVT DBF, @AR”), stack manipulation instruction (“PUSH AR” or “POP AR”), indirect branch instruction (“BR @AR”), and indirect subroutine call instruction (“CALL ...

Page 35

Bank Register (BANK) 5.3.1 Configuration of bank register Figure 5-3 shows the configuration of the bank register. As shown in this figure, the bank register consists of 4 bits of address 79H (BANK) of the system register. Note, however, ...

Page 36

Program Status Word (PSWORD) 5.4.1 Configuration of program status word Figure 5-4 shows the configuration of the program status word. As shown in this figure, the program status word consists of a total of 5 bits: the least significant ...

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Functions of program status word The program status word sets conditions, under which the ALU (Arithmetic Logic Unit) performs arithmetic or transfer operations, and indicates the results of the operations. Table 5-2 outlines the function of each flag of ...

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GENERAL REGISTERS (GR) 6.1 Outline of General Registers With the PD17073, the general registers are fixed at row address 0 of BANK0 on the data memory, and consist of 16 nibbles (16 4 bits) of 00H through 0FH. The ...

Page 39

Address Creation of General Register with Each Instruction The following paragraphs 6.2.1 and 6.2.2 describe how the address of the general register is created when each instruction is executed. For details of the operation of each instruction, refer to ...

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ALU (ARITHMETIC LOGIC UNIT) BLOCK 7.1 General Figure 7-1 shows the configuration of the ALU block. As shown in the figure, the ALU block consists of an ALU, temporary registers A and B, program status word, decimal adjuster circuit, ...

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Configuration and Function of Each Block 7.2.1 Functions of ALU The ALU performs arithmetic operation, logical operation, bit judgment, comparison, rotation, and transfer of 4- bit data as the instruction specified by the program. 7.2.2 Temporary registers A and ...

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Table 7-1. ALU Processing Instruction List ALU function Instruction Value of BCD flag Addition ADD m, # ADDC m, #n4 Subtraction SUB m, # SUBC m, #n4 Logical ...

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Table 7-2. Decimal Adjusted Data Hexadecimal addition Decimal addition Result of operation Result operation 0 0 0000B 0001B 0010B 0011B 0100B 0101B ...

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Notes on Using ALU 7.4.1 Notes on executing operation to program status word When an arithmetic operation is performed to the program status word, the result of the operation is stored in the program status word. The CY and ...

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PERIPHERAL CONTROL REGISTERS 8.1 Outline of Peripheral Control Registers Figure 8-1 outlines the peripheral control registers. Thirty-two 4-bit peripheral registers are available that control the peripheral hardware such as the PLL frequency synthesizer, serial interface, and intermediate frequency counter ...

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Configuration and Function of Peripheral Control Registers Figure 8-2 shows the configuration of the peripheral control registers. Table 8-1 lists the peripheral hardware control functions of the peripheral control registers. As shown in Figure 8-2, the peripheral control registers ...

Page 47

PD17072,17073 47 ...

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Figure 8-2. Configuration of Peripheral Control Registers (1/2) (BANK1) Column address 0 1 Row address Item LCD driver Basic timer 0 Name display carry register start register Note ...

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Figure 8-2. Configuration of Peripheral Control Registers (2/ INT pin Basic timer 1 Serial interface BEEP clock interrupt interrupt interrupt request select register request request register register register ...

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Table 8-1. Peripheral Hardware Control Functions of Peripheral Control Registers (1/4) Peripheral Control register hardware Name Address Read Write Stack Stack pointer (BANK1) R/W 0 – – – – – – – ...

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Table 8-1. Peripheral Hardware Control Functions of Peripheral Control Registers (2/4) Peripheral Control register hardware Name Address Read Write PLL PLL mode select (BANK1) R/W 0 – – – – – – ...

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Table 8-1. Peripheral Hardware Control Functions of Peripheral Control Registers (3/4) Peripheral Control register hardware Name Address Read Write A/D A/D converter (BANK1) R/W 0 – – – – – – – ...

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Table 8-1. Peripheral Hardware Control Functions of Peripheral Control Registers (4/4) Peripheral Control register hardware Name Address Read Write counter IF counter mode (BANK1) R/W IFCMD1 – – – – – ...

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DATA BUFFER (DBF) 9.1 General Figure 9-1 outlines the data buffer. The data buffer is located on the data memory and has the following two functions: (1) Reads constant data on program memory (table reference) (2) Transfers data with ...

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Data Buffer 9.2.1 Configuration of data buffer Figure 9-2 shows the configuration of the data buffer. As shown in this figure, the data buffer is configured of 16 bits of addresses 0CH-0FH of BANK0 on the data memory. Of ...

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Table reference instruction (“MOVT DBF, @AR”) When this instruction is executed, the contents of the program memory addressed by the contents of the address register are incorporated into the data buffer. The program memory addresses to which table reference ...

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GENERAL-PURPOSE PORT The general-purpose ports output high or low floating signals to external circuits, and reads high or low level signals from external circuits. 10.1 General Table 10-1 shows the relations between each port and port register. The general-purpose ...

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General-Purpose I/O Ports (P0B, P0C, P0D) 10.2.1 Configuration of I/O ports The configurations of the I/O ports are shown below. P0B (P0B3, P0B2, P0B1, P0B0) P0C (P0C1, P0C0) P0D (P0D3, P0D2 10.2.2 Use of I/O ...

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Control register of I/O port The port 0B bit I/O select register sets the input or output mode of each pin of P0B. The port 0C bit I/O select register sets the input or output mode of each pin ...

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Port 0C bit I/O select register Flag symbol Name Port 0C bit I select register ...

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To use I/O port in input mode The port pin to be used in the input mode is selected by the I/O select register of each port. The pin set in the input mode is floated (Hi-Z) and waits ...

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General-Purpose Input Ports (P1A) 10.3.1 Configuration of input ports The configuration of the input ports is illustrated below. P1A (P1A3, P1A2, P1A1, P1A0) To A/D converter V DD P1APLD3 High ON P1APLD2 resistance P1APLD1 P1APLD0 62 Write instruction Read ...

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... Nothing is changed even if a write instruction (such as MOV) is executed to the port register. Port 1A can be connected to or disconnected from a pull-down resistor bitwise by software. Whether the pull-down resistor is connected or disconnected is specified by the port 1A pull-down resistor select register. ...

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Reset status of input port (1) On power-ON reset All pins are specified as a input port. Pulled down internally. ( reset All pins are specified as a input port. The previous status of the pull-down resistor ...

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... Retains the contents of the output latch. The contents of the output latch are retained; therefore, the output data is not changed on execution of the clock stop instruction. Initialize the port through program as necessary. (4) In halt status The contents of the output latch are output. The contents of the output latch are retained; therefore, the output data is not changed in the halt status. ...

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INTERRUPT 11.1 General Figure 11-1 shows the outline of the interrupt block. As shown in this figure, the interrupt block temporarily stops the program under execution, and branches to an interrupt vector address according to an interrupt request output ...

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Interrupt Control Block An interrupt control block is available for each peripheral hardware. Each of these blocks detects the presence/ absence of an interrupt request, enables/disables the interrupt, and generates a vector address when the interrupt is accepted. 11.2.1 ...

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Figure 11-3. Configuration of Basic Timer 1 Interrupt Request Register Flag symbol Name Basic timer interrupt request T register Power-ON ...

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Interrupt enable flag (IPxxx) Each interrupt enable flag enables or disables the interrupt request of the corresponding peripheral hardware. So that an interrupt is accepted, all the following three conditions must be satisfied: • The interrupt must be enabled ...

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Vector address generator (VAG) When an interrupt request from peripheral hardware has been accepted, the vector address generator generates a branch address (vector address) to which the program execution branched. The vector addresses corresponding to each ...

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... Figure 11-7 illustrates the operations of the interrupt stack. When multiplexed interrupts have been accepted, the first contents saved to the stack are popped. If these contents are necessary, therefore, they must be saved through program. Figure 11-7. Operations of Interrupt Stack (a) If interrupt level does not exceed 1 ...

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Stack Pointer, Address Stack Register, and Program Counter The address stack register saves the return address to which the program execution is to restore when execution exits from an interrupt service routine. The stack pointer specifies the address of ...

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Accepting Interrupt 11.6.1 Interrupt accepting operation and priority An interrupt is accepted in the following sequence: (1) Each peripheral hardware issues an interrupt request signal to an interrupt request block when a certain condition is satisfied (for example, when ...

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Timing to accept interrupt Figure 11 timing chart illustrating how interrupts are accepted. (1) in this figure illustrate how one type of interrupt is accepted. (a) in (1) indicates the case where the interrupt request flag is ...

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Figure 11-8. Interrupt Accepting Timing Chart (1/2) (1) When one type of interrupt (e.g., rising edge of INT pin) is used (a) When there is no time to mask interrupt by interrupt enable flag (IPxxx) <1> ordinary instruction ...

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Figure 11-8. Interrupt Accepting Timing Chart (2/2) (2) When two or more interrupts are used (e.g., INT pin and basic timer 1) (a) Hardware priority MOV POKE EI Instruction WR, #0011B INTPM1, WR INTE INT pin IRQ flag Basic timer ...

Page 77

... The lower 1 bit of the bank register (BANK) is saved to the interrupt stack. Caution At this time, the contents of the program status word (PSWORD) are not saved. Save the contents of the program status word by software as necessary. (5) The contents of the vector address generator corresponding to the accepted interrupt are transferred to the program counter ...

Page 78

Exiting from Interrupt Service Routine To return to the service that was executed when the interrupt was accepted from the interrupt service routine, a dedicated instruction “RETI” is used. When this instruction is executed, the following processing is automatically ...

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External (INT Pin) Interrupts 11.9.1 Outline of external interrupts Figure 11-9 outlines the external interrupts. As shown in this figure, an interrupt request for an external interrupt is issued at the rising or falling edge of the signal input ...

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Figure 11-10. Configuration of Interrupt Edge Select Register Flag symbol Name Interrupt edge select register ...

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Table 11-2. Issuing Interrupt Request By Changing IEG Flag Changes in IEG flag INT pin status 1 0 Low level (falling) (rising) High level 0 1 Low level (rising) (falling) High level 11.9.3 Interrupt control block The level of a ...

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TIMER The timers are used to control the program execution time. 12.1 General As shown in this figure, the PD17013 is provided with the following two timers: • Basic timer 0 • Basic timer 1 The basic timer 0 ...

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Flip-flop and BTM0CY flag The flip-flop is set at fixed time intervals and its status is detected by the BTM0CY flag of the basic timer 0 carry register. The BTM0CY flag is a read-only flag, and is reset to ...

Page 84

Figure 12-2. Configuration of Basic Timer 0 Carry Register Flag symbol Name Basic timer 0 carry register Power-ON At Clock stop reset CE 12.2.3 Application example of basic timer 0 An example ...

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Error of basic timer 0 The time at which the BTM0CY flag detected must be shorter than the time at which the BTM0CY flag set (refer to 12.2.5 Notes on using basic timer ...

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Notes on using basic timer 0 (1) BTM0CY flag detection time interval The time interval at which the BTM0CY flag detected must be shorter than the time interval at which the flag set. ...

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Example Timer updating processing and BTM0CY flag detection time interval BTIMER: BANK1 SKT1 BTM0CY BR AAA Timer updating BR BTIMER AAA: Processing A BR BTIMER The following is the timing chart of the above program pin L H ...

Page 88

... However, because the BTM0CY flag is cleared to “0” result of reading the BTM0CY flag to detect a power failure, the set (1) status of the BTM0CY flag is overlooked once. Consequently necessary to update the watch timer if CE reset has been detected as a result of power failure detection. ...

Page 89

Internal pulse BTM0CY flag setting pulse L 1 BTM0CY flag 0 Program processing A C Program instruction <1> Power application Power-ON reset starts from address 0. ...

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If detection of BTM0CY flag overlaps with CE reset As described in (3), the CE reset is effected as soon as the BTM0CY flag has been set the BTM0CY flag read instruction happens to be executed ...

Page 91

Basic Timer 1 12.3.1 General Figure 12-7 outlines the basic timer 1. The basic timer 1 issues an interrupt request at fixed time interval and sets the IRQBTM1 flag to 1. The time interval of the IRQBTM1 flag is ...

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Figure 12-8. Configuration of Interrupt Edge Select Register Flag symbol Name Interrupt edge select register ...

Page 93

Application example of basic timer 1 A program example is shown below. Example M1 MEM 0.10H BTIMER1 DAT 0002H BR START ORG BTIMER1 ADD M1, #0001B SKT1 CY BR EI_RETI MOV M1, #0110B Processing A EI_RETI: EI RETI START: ...

Page 94

Error of basic timer 1 As described in 12.3.2, the interrupt generated by basic timer 1 is accepted each time the basic timer 1 interrupt pulse falls, if the EI instruction has been executed, and if the interrupt has ...

Page 95

Figure 12-9. Error of Basic Timer 1 (2/2) (b) When basic timer 1 interrupt pulse is changed Internal H pulse A L Internal H pulse Basic timer 1 interrupt pulse L 1 IRQBTM1 flag 0 1 IPBTM1 ...

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Notes on using basic timer 1 When creating a program, such as a program for watch, in which processing is always performed at fixed time intervals by using the basic timer 1 after the supply voltage has been once ...

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Figure 12-10. Timing Chart H CE pin L BTM0CY flag H setting pulse L H Basic timer 1 interrupt pulse L Basic timer 1 interrupt PD17072,17073 Because BTM0CY flag setting pulse rises, CE reset is effected here result, ...

Page 98

A/D CONVERTER 13.1 General Figure 13-1 outlines the A/D converter. The A/D converter compares an analog voltage input to the AD0 or AD1 pins with the internal compare voltage, judge the comparison result via software, and converts the analog ...

Page 99

Setting A/D Converter Power Supply The PD17073 has a power supply for the A/D converter. This power supply is also used for LCD display. When using the A/D converter, therefore, the A/D converter power supply must be set to ...

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Input Selector Block Figure 13-3 shows the configuration of the input selector block. The input selector block selects the pin to be used by using the A/D converter channel select register. Two or more pins cannot be used at ...

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Figure 13-4. Configuration of A/D Converter Channel Select Register Flag symbol Name A/D converter channel select register ...

Page 102

Compare Voltage Generator Block and Compare Block Figure 13-5 shows the configuration of the compare voltage generator block and compare block. The compare voltage generator block switches over the tap decoder by using 4-bit data set to the A/D ...

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Figure 13-6. Configuration of A/D Converter Compare Start Register Flag symbol Name A/D converter C compare start register Power-ON At Clock ...

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Figure 13-7. Configuration of A/D Converter Compare Result Detection Register Flag symbol Name A/D converter compare result detection register Power- Clock stop reset CE 104 Read/ Address ...

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Figure 13-8. Configuration of A/D Converter Reference Voltage Setting Register Flag symbol Name A/D converter reference ...

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Table 13-1. Set Value of A/D Converter Reference Voltage Setting Register and Compare Voltage A/D Converter reference voltage setting register set data Decimal Hexadecimal (DEC ...

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Comparison Timing Chart The ADCEN flag is automatically cleared to 0 when the comparison operation has been completed. The ADCSTRT flag is reset to 0 two instructions after the ADCSTRT flag has been set. At this point, the compare ...

Page 108

Using A/D Converter 13.7.1 Comparing one reference voltage The following shows a program example. Example To compare voltage input to AD0 pin > execution branches to AAA ADCIN REF BANK1 SET1 ADCON INITFLG ...

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Successive comparison by means of binary search The A/D converter can compare only one reference voltage at a time. Consequently, successive comparison must be executed through program in order to convert input voltages into digital signals. If the processing ...

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Flowchart of binary search START Initial setting (A/D converter reference voltage setting register) = #1000B ADCCMP = 1? N Reset ADCRFSEL3 flag Set ADCRFSEL2 flag ADCCMP = 1? N Reset ADCRFSEL2 flag Set ADCRFSEL1 flag ADCCMP = 1? N ...

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Program example of binary search START: BANK1 INITFLG NOT ADCCH1, ADCCH0 INITFLG P1APLD2 INITFLG NOT ADCRFSEL3, ADCRFSEL2, ADCRFSEL1, ADRFSEL0 SET1 ADCSTRT NOP NOP SKF1 ADCCMP SET1 ADCRFSEL3 CLR1 ADCRFSEL2 SET1 ADCSTRT NOP NOP SKF1 ADCCMP SET1 ADCRFSEL2 CLR1 ADCRFSEL1 ...

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SERIAL INTERFACE 14.1 General Figure 14-1 shows the outline of the serial interface. This serial interface is of two-wire/three-wire serial I/O type. The former type uses SCK and SO1/SI pins. The latter uses SCK, SI, and SO0 pins. Figure ...

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Clock Input/Output Control Block and Data Input/Output Control Block The clock input/output control block and data input/output control block select the operation mode of the serial interface (2-wire or 3-wire mode), control the transmit/receive operation, and select a shift ...

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Figure 14-3. Configuration of Serial I/O Mode Select Register Flag symbol Name Serial I mode select register ...

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Table 14-1. Set Status of Each Pin By Control Flags Control flags of serial interface Communi- S Serial S Serial I I cation O I/O O interface S H mode select pin setting 3-wire serial Note ...

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Setting 2-/3-wire mode The serial interface uses two pins in the two-wire mode: SCK/P0B2 and SO1/SI/P0B3. The SCK/P0B2 pin is used as a shift clock input/output pin, and the SO1/SI/P0B3 pin is used as a serial data input/ output ...

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Presettable Shift Register The presettable shift register is an 8-bit shift register that writes serial-out data and reads serial-in data. Writing/reading data to/from the presettable shift register is performed by PUT and GET instructions via data buffer. The presettable ...

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Serial Interface Operation The timing of each operation of the serial interface is described below. This timing is applicable to both 2-wire and 3-wire modes. 14.7.1 Timing chart Figure 14-5 shows a timing chart. Figure 14-5. Timing Chart of ...

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Wait operation and note When the wait status has been released, serial data is output at the next falling edge of the clock (transmission operation), and the wait released status continues until eight clocks are counted. After the eight ...

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Figure 14-6. Shift Clock Generation Timing of Serial Interface (1/4) Shift clock (37.5 kHz) Wait status Initialization Wait released Shift clock (18.75 kHz) Wait status Initialization Wait released Shift clock (12.5 kHz) Wait status Initialization Wait released (2) When wait ...

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When forced wait status is set during wait status Figure 14-6. Shift Clock Generation Timing of Serial Interface (3/4) Contents of output latch Shift clock Wait period Forced wait by SIOTS (c) When forced wait status is set while ...

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Notes on Setting and Reading Data Use the “PUT SIOSFR, DBF” instruction to set data to the presettable shift register. Use the “GET DBF, SIOSFR” instruction to read data. Set or read the data in the wait status. While ...

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Operational Outline of Serial Interface Tables 14-3 and 14-4 outline the operations of the serial interface. Table 14-3. Operation in 3-wire Serial I/O Mode Operation mode Slave operation (SIOCK1 = SIOCK0 = 0) Item During wait (SIOTS = 0) ...

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Table 14-4. Operation in Two-Wire Serial I/O Mode Operation mode Slave operation (SIOCK1 = SIOCK0 = 0) Item During wait (SIOTS = 0) Status of SCK/P0B2 • When P0BBIO2 = 0 each pin General-purpose input port • When P0BBIO2 = ...

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Status on Reset 14.10.1 At power-ON reset P0B2/SCK and P0B3/SI/SO1 pins are set in the general-purpose input port mode. P1C0/SO0 pin is set in the general-purpose port. The contents of the presettable shift register are undefined. 14.10.2 At clock ...

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... HF (High Frequency), and VHF (Very High Frequency) bands to a fixed frequency, by means of phase difference comparison. 15.1 General Figure 15-1 outlines the PLL frequency synthesizer. By connecting an external lowpass filter (LPF) and voltage controlled oscillator (VCO), the PLL frequency synthesizer can be configured. The PLL frequency synthesizer divides a signal input from the VCOH or VCOL pin by using a programmable divider, and outputs the phase difference between the signal and the reference frequency from the EO pin ...

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... The selected pin is at the intermediate potential (approx. 1/2V These pins have an AC amplifier at the input stage; therefore, cut the DC component of the input signal by connecting a capacitor in series. As the division method, DC division method or pulse swallow method can be selected. The programmable divider performs frequency division according to the values set to the swallow counter and programmable counter ...

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Table 15-1. Input Pins and Division Modes Division mode Pin Input frequency Direct division (MF) VCOL Pulse swallow VCOL (HF) Pulse swallow VCOH (VHF) Figure 15-3. Configuration of PLL Mode Select Register Flag symbol Name PLL mode ...

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Outline of each division mode (1) Direct division mode (MF) In this mode, the VCOL pin is used. The VCOH pin is floated. The frequency of the input signal is divided only by the programmable counter in this mode. ...

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Programmable divider, PLL data register, and PLL data set register A division value is set to the swallow counter and programmable counter by the PLL data register. The value set by the PLL data register is transferred by the ...

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Figure 15-4. Configuration of PLL Data Register Name Address 67H 68H Bit ...

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Figure 15-5. Configuration of PLL Data Set Register Flag symbol Name PLL data set register Power-ON At Clock stop reset CE 132 Read/ Address b b Write ...

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Reference Frequency Generator Figure 15-6 shows the configuration of the reference frequency generator. The reference frequency generator divides 75 kHz output by the crystal oscillator to generate the reference frequency “f ” of the PLL frequency synthesizer ...

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Figure 15-7. Configuration of PLL Reference Frequency Select Register Flag symbol Name b 3 PLL reference frequency 0 select register Power- Clock stop reset CE reset Remark When the PLL reference frequency select register is set to “PLL ...

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Phase Comparator ( -DET), Charge Pump, and Unlock FF 15.4.1 Configurations of phase comparator, charge pump, and unlock FF Figure 15-8 shows the configurations of the phase comparator, charge pump, and unlock FF. The phase comparator compares the output ...

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Functions of phase comparator As shown in Figure 15-8, the phase comparator compares the output frequency of the programmable divider “f against reference frequency “f ”, and outputs UP or DOWN request signal. r That is ...

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Charge pump As shown in Figure 15-8, the charge pump outputs the UP and DOWN request signals from the phase comparator to the error out pin (EO). Therefore, the relations among the outputs of the error out pins, divided ...

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Table 15-2. Instructions to Reset PLL Unlock FF Register Mnemonic ADD ADDC SUB SUBC AND OR XOR SKE SKEG SKLT SKNE Note When the row address and 0DH is written to r. Remark m = 6DH ...

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PLL Disable Status The PLL frequency synthesizer stops its operation (i.e., is disabled) while the CE pin is low. Similarly, the synthesizer stops when the “PLL disable status” is selected by the PLL reference frequency select register or PLL ...

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... Use of PLL Frequency Synthesizer To control the PLL frequency synthesizer, the following data are necessary: (1) Division mode : direct division (MF) or pulse swallow (HF, VHF) (2) Pin to be used : VCOL or VCOH (3) Reference frequency : f r (4) Division value : N The following paragraphs 15.6.1 through 15.6.3 describe how to set the above data in each division mode (MF, HF, or VHF) ...

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Pulse swallow mode (HF) (1) Selecting division mode Select the pulse swallow mode by the PLL mode select register. (2) Pin to be used The VCOL pin is enabled when the pulse swallow mode is selected. (3) Setting reference ...

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Pulse swallow mode (VHF) (1) Selecting division mode Select the pulse swallow mode by the PLL mode select register. (2) Pin to be used The VCOH pin is enabled when the pulse swallow mode is selected. (3) Setting of ...

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Status on Reset 15.7.1 On power-ON reset The PLL mode select register is initialized to 0000B; therefore, the PLL disable status is set. 15.7.2 On clock stop The PLL disable status is set when the CE pin goes low. ...

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INTERMEDIATE FREQUENCY (IF) COUNTER 16.1 Outline of Intermediate Frequency (IF) Counter Figure 16-1 outlines the IF counter. The IF counter is mainly used to detect broadcasting stations, and is used to count the intermediate frequency (IF) output from a ...

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IF Counter Input Select Block and Gate Time Control Block Figure 16-2 shows the configuration of the IF counter input select block and gate time control block. The IF counter input select block selects, by using the IF counter ...

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Figure 16-3. Configuration of IF Counter Mode Select Register Flag symbol Name counter mode select register ...

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Start Control Block and IF Counter 16.3.1 Configuration of start control block and IF counter Figure 16-4 shows the configuration of the start control block and IF counter. The start control block starts counting of the frequency counter and ...

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Figure 16-5. Configuration of IF Counter Control Register Flag symbol Name counter control register Power- Clock stop ...

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Figure 16-6. Configuration of IF Counter Gate Status Detection Register Flag symbol Name counter gate status detection register Power- Clock stop reset CE Caution When the ...

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Gate operation of IF counter function (1) When gate time is set shown below, the gate is opened for starting from the rising edge of an internal ...

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Figure 16-7. Configuration of IF Counter Data Register Data buffer DBF3 DBF2 DBF1 Transfer data 16 Peripheral register Name counter Valid ...

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Using IF Counter The following sections 16.4.1 through 16.4.3 describe how to use the hardware of the IF counter, program example, and count error. 16.4.1 Using hardware of IF counter Figure 16-8 shows the block diagram when the P0D2/AMIFC ...

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Program example of IF counter A program example of the IF counter is shown below. As shown in this example, make sure that a wait time of a certain length elapses after an instruction that specifies the P0D2/AMIFC or ...

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Status at Reset 16.5.1 Power-ON reset The P0D3/FMIFC/AMIFC and P0D2/AMIFC pins are set in the general-purpose input port mode. The contents of the output latch are “0”. 16.5.2 On execution of clock stop instruction The P0D3/FMIFC/AMIFC and P0D2/AMIFC pins ...

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BEEP 17.1 Configuration and Function of BEEP Figure 17-1 outlines BEEP. BEEP outputs a clock of 1.5 kHz or 3 kHz from the BEEP pin. The output select block selects, by using the BEEP0CK0 and BEEP0CK1 flags of the ...

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Output Wave Form of BEEP (1) Output wave 1.5 kHz and kHz BEEP (f = 1.5 kHz) 333.3 s 333.3 s BEEP ( kHz) 133.3 s 200 s Example Program to ...

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Status at Reset 17.3.1 At power-ON reset The BEEP pin is set in the general-purpose output port mode, and outputs a low level. The value of the latch of the output port is “0”. 17.3.2 On execution of clock ...

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LCD CONTROLLER/DRIVER The LCD (Liquid Crystal Display) controller/driver can display an LCD dots by a combination of command signal and segment signal outputs. 18.1 Outline of LCD Controller/Driver Figure 18-1 outlines the LCD controller/driver. The ...

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... REG 0, CAP LCD Figure 18-2 shows an example of configuration of the doubler circuit. To use a voltage of 3.1 V (TYP.), connect as shown in Figure 18-2. To operate the doubler circuit, the LCDEN flag of the LCD display start register must be set to “1”. Unless this flag is set to “1”, the LCD drive voltage generation block does not operate. For the LCDEN flag, refer to 18.4 Common Signal Output and Segment Signal Output Timing Control Blocks ...

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LCD Segment Register The LCD segment register sets dot data to turn on or turn off dots on the LCD. Figure 18-3 shows the location in the data memory and configuration of the LCD segment register. Because the LCD ...

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Address 41H 42H 43H Symbol LCDD14 LCDD13 LCDD12 Bit ...

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Common Signal Output and Segment Signal Output Timing Control Blocks Figure 18-5 shows the common signal output and segment signal output timing control blocks. The common signal output timing control block controls the common signal output timing of the ...

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Figure 18-6. Configuration of LCD Driver Display Start Register Flag symbol Name LCD driver display start 0 0 register Power- Clock stop reset CE Remark R: Retained Cautions 1. Bit 3 of the ...

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Figure 18-7. Common Signal and Segment Signal Output Waves Common signal 1 frame (16 ms) COM0 pin COM1 pin COM2 pin COM3 pin Segment signal (example extinguishes LCDn pin lights ...

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... Using LCD Controller/Driver Figure 18-8 shows an example of wiring of an LCD panel An example of a program that lights the 7 segments connected to LCD0 and LCD1 pins shown in Figure 18-8 is given below. Example PMN0 MEM 0.01H CH FLG LCDD0.3 LCDDATA: DW 0000000000000000B DW 0000000000000110B DW 0000000010110101B DW 0000000010100111B DW 0000000001100110B DW 0000000011100011B DW 0000000011110011B DW 0000000010000110B ...

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Figure 18-8. Example of Wiring of LCD Panel Correspondence of Segment and Common Pins, and LCD Panel Display Segment Pin ...

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Status at Reset 18.7.1 At power-ON reset The LCD0 through LCD14 pins output a low level. The COM0 through COM3 pins also output a low level. Therefore, the LCD display is OFF. The contents of the LCD segment register ...

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STANDBY The standby function is used for the purpose of reducing the current consumption of the device when the device is in the backup status. 19.1 General Figure 19-1 shows the outline of the standby block.The standby function is ...

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Figure 19-1. Outline of Standby Block Halt block Interrupt control block Basic timer 0 P1A3/AD1 P1A2/AD0 P1A1 P1A0 Clock stop block CE flag CE X OUT X IN Remark CE flag (bit pin status detection register. Refer ...

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Halt Function 19.2.1 General The halt function is to stop the operation clock of the CPU by executing the “HALT h” instruction. When this instruction has been executed, the program is stopped and is not executed unless the halt ...

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... With the key input specified as the halt release condition, the halt mode is released when a high-level signal is input to any one of the P1A0, P1A1, P1A2/AD0, and P1A3/AD1 pin. However, halt mode cannot be released by a pin disconnected to the pull-down resistor. (1) When using general-purpose output port as key source signal ...

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Releasing halt status with basic timer 0 To release the halt condition by using the basic timer 0, use the “HALT 0010B” instruction. When it has been set that the halt status released by the basic ...

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Releasing halt status by interrupt To release the halt status by interrupt, use the “HALT 1000B” instruction. There are three interrupt sources available as explained in 11. INTERRUPT. Therefore, the interrupt by which the halt status ...

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Example 1. Example of program when EI instruction is executed HLTINT DAT 1000B INTTM DAT 0002H INTPIN DAT 0003H START: BR MAIN ORG INTTM BR INTTIMER ORG INTPIN Processing A BR EI_RETI INTTIMER: Processing B EI_RETI: EI RETI MAIN: BANK1 ...

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Example 2. Example of program when DI instruction is executed HLTINT DAT 1000B START: DI BANK1 SET2 IPBTM1, IP SET1 BTM1CK LOOP: HALT HLTINT SKT1 IRQ BR INTBTM1 CLR1 IRQ Processing A INTBTM1: SKT1 IRQBTM1 BR LOOP CLR1 IRQBTM1 Processing ...

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Caution When executing the HALT instruction that is released when an interrupt request flag (IRQ for which the corresponding interrupt enable flag (IP immediately before the HALT instruction. When the NOP instruction is described immediately before the HALT instruction, time ...

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When two or more release conditions are specified When two or more halt release conditions are specified, the halt mode is released if any one of the specified conditions is satisfied. The following example shows how the condition is ...

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Clock Stop Function The clock stop function stops the 75 kHz crystal resonator when the “STOP s” instruction (clock stop status) is executed. Therefore, the current dissipation of the device is reduced maximum (T As the ...

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Figure 19-3. Releasing Clock Stop by CE Reset pin pin OUT L If the clock stop instruction is not used, the operation is performed as follows ...

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... Notes on using clock stop instruction The clock stop instruction (“STOP s”) is valid only when the CE pin is at the low level. Therefore necessary to design program taking into consideration the chance that the “STOP s” instruction executed when the CE pin happens the high level. ...

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Device Operations in Halt and Clock Stop Statuses Table 19-1 shows the operations of the CPU and peripheral hardware in the halt and clock stop statuses. In the halt status, all the peripheral hardware continue the normal operation, except ...

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Table 19-1. Device Operations in Halt and Clock Stop Statuses Hardware peripheral CE pin = high level In halt status Program counter Stops at address before HALT instruction System register Retained Peripheral register Retained Timer Normal operation PLL frequency synthe- ...

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... Initialize frequency counter by pro- gram as necessary because it is not automatically disabled even when CE pin is low. PD17072,17073 Clock stop status 183 ...

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Table 19-2. Pin Status in Halt and Clock Stop Statuses and Notes (2/2) Pin function Pin symbol When these pins are used as general-purpose LCD segment LCD14 output port pins, the same points as those of | the general-purpose output ...

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Device Control Function by CE Pin The CE pin has the following functions by using the input level and rising edge of a signal input from an external source: (1) PLL frequency synthesizer (2) Making clock stop instruction valid ...

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Inputting signal to CE pin The CE pin does not accept a low- or high-level signal less than 200 s in order to protect the system from malfunctioning due to noise. The level of the signal input to the ...

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Low-Speed Mode Function The PD17073 can slow down the CPU clock when “1” is written to the SYSCK flag of the system clock select register. This function is called a low-speed mode function. The time required to execute one ...

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RESET The reset function is to initialize the device operation. 20.1 Configuration of Reset Block Figure 20-1 shows the configuration of the reset block. The device can be reset in two ways: by means of power-ON reset (or V ...

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Reset Function The power-ON reset is effected when supply voltage V when the CE pin goes high from low. The power-ON reset is to initialize the program counter, stack, system register, basic timer 0 carry FF and control register, ...

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CE Reset The CE reset is effected by making the CE pin high. When the CE pin goes high, the RESET signal is output in synchronization with the rising edge of the next basic timer 0 carry FF setting ...

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CE reset when clock stop mode (STOP s instruction) is used Figure 22-3 shows the operation. When the clock stop mode is used, the IRES, RES, and RESET signals are output at the point where the “STOP s” instruction ...

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Example 1. R1 MEM 0.01H R2 MEM 0.02H R3 MEM 0.03H R4 MEM 0.04H M1 MEM 0.11H M2 MEM 0.12H START: Key input processing R1 Key A contents R2 Key B contents SET2 CMP, Z SUB R1, M1 SUB R2, ...

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Example 2. R1 MEM 0.01H R2 MEM 0.02H R3 MEM 0.03H R4 MEM 0.04H M1 MEM 0.11H M2 MEM 0.12H CHANGE FLG 0.13H.0 START: Key input processing R1 Key A contents R2 Key B contents SKT1 CHANGE BR SECURITY_CHK ST ...

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Power-ON Reset Power-ON reset is effected by raising the supply voltage V clear voltage). Power-ON clear voltage is described in 20.4.1. If the supply voltage V is lower than the power-ON clear voltage, a power-ON clear signal (POC) is ...

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Power-ON clear voltage The power-ON clear voltage differs as follows, depending on the CPU operating temperature range and operating conditions + 1.6 V MAX. (when CPU is operating and PLL frequency synthesizer and ...

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Figure 20-5. Power-ON Reset and Supply Voltage (a) During CPU operation (including halt status 1 OUT L H Power-ON clear signal L Normal operation (b) ...

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Relations between CE Reset and Power-ON Reset There is a possibility that power-ON reset and CE reset are effected simultaneously when the supply voltage V is applied for the first time. The reset operations at this time are described ...

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Figure 20-6. Relations between Power-ON Reset and CE Reset (T = –20 to +70 C, when CPU, PLL, A/D are operating) A (a) When VDD and CE pins rises simultaneously ...

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Power Failure Detection The power failure detection feature is used to judge, when the device has been reset, whether the reset has been effected by application of supply voltage V Because the contents of the data memory and output ...

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Figure 20-8. Status Transition of BTM0CY Flag CE = low <2> Setting BTM0CY flag inhibited <4> <5> STOP 0 Normal Clock stop operation <10> SKT1 BTM0CY or SKF1 BTM0CY <12> <13> STOP 0 Normal Clock stop operation Setting BTM0CY flag ...

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