UPD17073 NEC, UPD17073 Datasheet - Page 195

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

20.4.1 Power-ON clear voltage
conditions:
not exceed these maximum values.
20.4.2 Power-ON reset during normal operation
supply voltage V
is stopped.
of 125 ms or more.
halt status set by the halt instruction.
20.4.3 Power-ON reset in clock stop mode
voltage V
or more.
20.4.4 Power-ON reset when supply voltage V
(T
and the program starts from address 0000H after a halt of 125 ms or more.
A
The power-ON clear voltage differs as follows, depending on the CPU operating temperature range and operating
T
T
T
The above values are the maximum values, and the actual power-ON clear voltage must be in a range that does
The power-ON clear voltage during the CPU operation is the same as that in the clock stop status.
In the description below, the power-ON clear voltage is assumed to be 1.8 V.
Figure 20-5 (a) shows the operation.
As shown in this figure, the power-ON clear signal is output regardless of the input level of the CE pin when the
When the supply voltage V
The CPU operation includes when the clock stop instruction is not used, and power-ON clear voltage is 1.8 V during
Figure 20-5 (b) shows the operation.
As shown in this figure, the power-ON clear signal is output and the device operation is stopped when the supply
However, because the clock stop mode is set, the operation of the device seems not to be changed.
When the supply voltage V
Figure 20-5 (c) shows the operation.
As shown in this figure, the power-ON clear signal is output until the supply voltage V
When the supply voltage V
= –20 to +70 C, CPU, PLL, A/D are operating).
A
A
A
= 0 to +70 C
= –10 to +70 C : 1.7 V MAX. (when CPU is operating and PLL frequency synthesizer and A/D converter stop)
= –20 to +70 C : 1.8 V MAX. (when CPU, PLL frequency synthesizer, and A/D converter are operating)
DD
drops below 1.7 V (T
DD
drops below 1.8 V (T
: 1.6 V MAX. (when CPU is operating and PLL frequency synthesizer and A/D converter stop)
DD
DD
DD
rises beyond 1.8 V again, the program starts from address 0000H after a halt status
rises beyond 1.8 V, the program starts from address 0000H after a halt of 125 ms
exceeds the power-ON clear voltage, the crystal oscillator circuit starts operating,
A
= –20 to +70 C, when CPU, PLL, A/D are operating).
A
= –20 to +70 C, when CPU, PLL, A/D are operating), and the device operation
DD
rises from 0 V
DD
PD17072,17073
rises from 0 V to 1.8 V
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