UPD17073 NEC, UPD17073 Datasheet - Page 131

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

Direct division
Pulse swallow
mode
Remark On power application and at power-ON reset, the contents of the PLL data register are undefined. On
Address
Name
mode
Data
Bit
execution of the clock stop instruction and at CE reset, the contents of the PLL data register are retained.
b
P
R
L
L
1
7
3
b
R
P
L
L
1
6
Valid bit: 12 bits (direct division mode)
67H
2
b
P
R
L
L
1
5
1
Valid bit: 17 bits (in pulse swallow mode)
b
P
R
L
L
1
4
0
b
R
P
L
L
1
3
2
3
12
15 (00FH)
16 (010H)
Figure 15-4. Configuration of PLL Data Register
–1 (FFFH)
b
P
R
L
L
1
2
68H
2
0
x
|
|
|
2
b
P
R
1023 (03FFH)
1024 (0400H)
L
L
1
1
17
1
–1 (1FFFFH)
b
P
R
L
L
1
0
0
0
x
PLL data register
|
|
|
b
R
P
L
L
9
3
BANK1
b
P
R
L
L
8
69H
2
b
P
R
L
L
7
1
b
R
P
L
L
6
0
b
P
R
L
L
5
3
b
P
R
don't care
don't care
L
L
4
6AH
2
b
P
R
L
L
3
1
b
R
P
L
L
2
0
b
P
R
L
L
1
3
Sets division ratio of PLL frequency synthesizer
Sets division ratio of PLL frequency synthesizer
b
Setting prohibited
Division ratio N : N = x
Setting prohibited
Division ratio N : N = x
0
6BH
2
b
0
1
b
0
0
Fixed to “0”
PD17072,17073
131