HD64336901G Renesas Technology, HD64336901G Datasheet - Page 89

• Manufacturer Part Number: HD64336901G
• Description: (HD64xxx Series) 16-BIT MICROCONTROLLER
• Manufacturer: Renesas Technology

When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 19.1,
Register Addresses (Address Order).
Table 4.1
4.1.2
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
ROM space
RAM space
I/O register with 8-bit data bus
width
I/O register with 16-bit data
bus width
Bit
7
6
5 to 0
Address Break Status Register (ABRKSR)
Bit Name
ABIF
ABIE
—
Access and Data Bus Used
Initial
Value
All 1
0
0
R/W
R/W
—
R/W
Even Address Odd Address
Upper 8 bits
Upper 8 bits
Upper 8 bits
Upper 8 bits
Word Access
Description
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
When this bit is 1, an address break interrupt request is
enabled.
Reserved
These bits are always read as 1.
Address Break Interrupt Flag
Address Break Interrupt Enable
Lower 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
Rev. 1.00, 11/03, page 61 of 376
Even Address Odd Address
Upper 8 bits
Upper 8 bits
Upper 8 bits
—
Byte Access
Upper 8 bits
Upper 8 bits
Upper 8 bits
—