HD64336901G Renesas Technology, HD64336901G Datasheet - Page 281

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HD64336901G

Manufacturer Part Number
HD64336901G
Description
(HD64xxx Series) 16-BIT MICROCONTROLLER
Manufacturer
Renesas Technology
Datasheet
15.5
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun error. Table 15.3 shows the
contents of each interrupt request.
Table 15.3 Interrupt Requests
When interrupt conditions described in table 15.3 are 1 and the I bit in CCR is 0, the CPU
executes an interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.
Interrupt Request
Transmit Data Empty
Transmit End
Receive Data Full
STOP Recognition
NACK Receive
Arbitration
Lost/Overrun Error
Interrupts
TXI
TEI
STPI
Abbreviation
RXI
NAKI
Interrupt Condition
(TDRE=1) (TIE=1)
(TEND=1) (TEIE=1)
(RDRF=1) (RIE=1)
(STOP=1) (STIE=1)
{(NACKF=1)+(AL=1)}
(NAKIE=1)
Rev. 1.00, 11/03, page 253 of 376
I
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2
C Mode
Clocked
Synchronous
Mode
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