HD64336901G Renesas Technology, HD64336901G Datasheet - Page 205

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HD64336901G

Manufacturer Part Number
HD64336901G
Description
(HD64xxx Series) 16-BIT MICROCONTROLLER
Manufacturer
Renesas Technology
Datasheet
12.5.7
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure
12.22 shows the timing of the IMFA to IMFD flag setting at input capture.
12.5.8
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 12.23 shows the status flag clearing timing.
Timing of IMFA to IMFD Setting at Input Capture
Timing of Status Flag Clearing
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture
Input capture
signal
TCNT
GRA to GRD
IMFA to IMFD
IRRTW
Address
Write signal
IMFA to IMFD
IRRTW
Figure 12.23 Timing of Status Flag Clearing by CPU
N
TSRW write cycle
TSRW address
T1
T2
N
Rev. 1.00, 11/03, page 177 of 376

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