HD64336901G Renesas Technology, HD64336901G Datasheet - Page 82
HD64336901G
Manufacturer Part Number
HD64336901G
Description
(HD64xxx Series) 16-BIT MICROCONTROLLER
Manufacturer
Renesas Technology
Datasheet
1.HD64336901G.pdf
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3.4.2
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For direct transfer interrupt requests generated by execution of a
SLEEP instruction, this function is included in IRR1 and IENR1.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit
is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable
bit.
3.4.3
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request
Rev. 1.00, 11/03, page 54 of 376
signal is sent to the interrupt controller.
Internal Interrupts
Interrupt Handling Sequence
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
Figure 3.1 Reset Sequence
Vector fetch
Reset cleared
(2)
(1)
Internal
processing
Initial program
instruction prefetch
(2)
(3)
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