HD64336901G Renesas Technology, HD64336901G Datasheet - Page 213

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HD64336901G

Manufacturer Part Number
HD64336901G
Description
(HD64xxx Series) 16-BIT MICROCONTROLLER
Manufacturer
Renesas Technology
Datasheet
13.3
The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD
starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is
generated. The internal reset signal is output for a period of 256
writable counter, it starts counting from the value set in TCWD. An overflow period in the range
of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. When the
watchdog timer is not used, stop TCWD counting by writing 0 to B2WI and WDON
simultaneously while the TCSRWE bit in TCSRWD is set to 1. (To stop the watchdog timer, two
write accesses to TCSRWD are required.)
Figure 13.2 shows an example of watchdog timer operation.
Example:
Operation
Internal reset
signal
count value
TCWD
With 30ms overflow period when
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
H'FF
H'00
4
8192
10
H'F1
Figure 13.2 Watchdog Timer Operation Example
6
30
H'F1 written
to TCWD
10
–3
= 14.6
H'F1 written to TCWD
= 4 MHz
Rev. 1.00, 11/03, page 185 of 376
256
RC
clock cycles. As TCWD is a
Reset generated
RC
TCWD overflow
clock cycles

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