HD64336901G Renesas Technology, HD64336901G Datasheet - Page 83

• Manufacturer Part Number: HD64336901G
• Description: (HD64xxx Series) 16-BIT MICROCONTROLLER
• Manufacturer: Renesas Technology

2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for
3. The CPU accepts the NMI or address break without depending on the I bit value. Other
4. If the CPU accepts the interrupt after processing of the current instruction is completed,
5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address
6.
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
the interrupt handling with the highest priority at that time according to table 3.1. Other
interrupt requests are held pending.
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interrupt exception handling.
Next, the CPU generates the vector address corresponding to the accepted interrupt, and
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.
SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
[Legend]
PC H :
PC L :
CCR:
SP:
Notes:
Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer
* Ignored when returning from the interrupt handling routine.
PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
Register contents must always be saved and restored by word length, starting from
an even-numbered address.
Prior to start of interrupt
Figure 3.2 Stack Status after Exception Handling
exception handling
Stack area
saved to stack
PC and CCR
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
After completion of interrupt
exception handling
CCR
CCR
PCH
PCL
Rev. 1.00, 11/03, page 55 of 376
*
Even address