HD64336901G Renesas Technology, HD64336901G Datasheet - Page 252

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HD64336901G

Manufacturer Part Number
HD64336901G
Description
(HD64xxx Series) 16-BIT MICROCONTROLLER
Manufacturer
Renesas Technology
Datasheet
14.8.4
In asynchronous mode, SCI3 operates on a basic clock with a frequency of 16 times the transfer
rate. In reception, SCI3 samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
basic clock as shown in figure 14.20. Thus, the reception margin in asynchronous mode is given
by formula (1) below.
Legend N : Ratio of bit rate to clock (N = 16)
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Rev. 1.00, 11/03, page 224 of 376
M = (0.5 –
D : Clock duty (D = 0.5 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
2N
Figure 14.20 Receive Data Sampling Timing in Asynchronous Mode
1
) –
16)}
D – 0.5
N
100 [%] = 46.875%
0
– (L – 0.5) F
8 clocks
Start bit
16 clocks
7
100(%)
15 0
D0
7
... Formula (1)
15 0
D1

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