HD64336901G Renesas Technology, HD64336901G Datasheet - Page 126

no-image

HD64336901G

Manufacturer Part Number
HD64336901G
Description
(HD64xxx Series) 16-BIT MICROCONTROLLER
Manufacturer
Renesas Technology
Datasheet
7.2.3
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
7.2.4
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, and EBR1.
Rev. 1.00, 11/03, page 98 of 376
Bit
7, 6
5
4
3
2
1
0
Bit
7
6 to 0
Bit Name
EB5
EB4
EB3
EB2
EB1
EB0
Bit Name
FLSHE
Flash Memory Enable Register (FENR)
Erase Block Register 1 (EBR1)
Initial
Value
All 0
0
0
0
0
0
0
Initial
Value
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0.
When this bit is set to 1, 4 kbytes of H'2000 to H'2FFF will
be erased.
When this bit is set to 1, 4 kbytes of H'1000 to H'1FFF will
be erased.
When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will
be erased.
When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will
be erased.
When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will
be erased.
When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will
be erased.
Description
Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers cannot
be accessed when this bit is set to 0.
Reserved
These bits are always read as 0.

Related parts for HD64336901G