HD64336901G Renesas Technology, HD64336901G Datasheet - Page 259

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HD64336901G

Manufacturer Part Number
HD64336901G
Description
(HD64xxx Series) 16-BIT MICROCONTROLLER
Manufacturer
Renesas Technology
Datasheet
15.3.3
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control,
and selects the transfer bit count.
Bit Bit Name
7
6
5, 4
3
MLS
WAIT
BCWP
I
2
C Bus Mode Register (ICMR)
Initial Value R/W Description
0
0
All 1
1
R/W MSB-First/LSB-First Select
R/W Wait Insertion Bit
R/W BC Write Protect
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
In master mode with the I
whether to insert a wait after data transfer except the
acknowledge bit. When WAIT is set to 1, after the fall of the
clock for the final data bit, low period is extended for two
transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no wait
inserted.
The setting of this bit is invalid in slave mode with the I
format or with the clocked synchronous serial format.
Reserved
These bits are always read as 1.
This bit controls the BC2 to BC0 modifications. When
modifying BC2 to BC0, this bit should be cleared to 0 and
use the MOV instruction. In clock synchronous serial mode,
BC should not be modified.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.
2
2
C bus format, this bit selects
C bus format is used.
Rev. 1.00, 11/03, page 231 of 376
2
C bus

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