TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 79

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
5.34
Exchange Contents
Exchange Digit
Push
Pop
XCH
XCH
XCHD
PUSH
PUSH
POP
POP
Note :
1.
2.
Mnemonic
Mnemonic
A shaded cell denotes an instruction in the C51 Architecture.
If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
A, Rn
A, dir8
A, @Ri
A, @Ri
dir8
#data
#data16
Rm
WRj
DRk
Dir
Rm
WRj
DRk
<dest> <src>
<dest>, <src>
Table 5.42. Summary of Exchange, Push and Pop Instructions
XCh <dest>, <src>
XCHD <dest>, <src>
PUSH <src>
POP <dest>
Acc and reg
Acc and direct addr
Acc and on-chip RAM (8-bit addr)
Acc and low nibble in on-chip RAM (8-bit
addr)
Push direct byte onto stack
Push immediate data onto stack
Push 16-bit immediate data onto stack
Push byte reg onto stack
Push word reg onto stack
Push double word reg onto stack
Pop direct byte from stack
Pop byte reg from stack
Pop word reg from stack
Pop double word reg from stack
Notes
Notes
A
A3:0
SP
dest
src opnd
SP +1; (SP)
(SP); SP
on-chip RAM bits 3:0
Bytes
Binary Mode
1
2
1
1
2
4
5
3
3
3
2
3
3
3
States
3
3/3
10
SP –1
3
4
4
2
4
5
4
6
3
5
9
(2)
src
Rev. C – May 7, 1999
Bytes
Source Mode
2
2
2
2
2
3
4
2
2
2
2
2
2
2
States
3
3/3
4
5
5
2
3
5
3
5
9
2
4
8
(2)