TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 41

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
4.6.7.2. Computation of Worst Case Latency with Variables
Worst-case latency calculations assume that the longest TSC80251 instruction used in the program must fully execute
prior to a context switch. The instruction execution time is reduced by one state with the assumption the instruction
state overlaps the request state (therefore, 16-bit DIV is 21 states -1 = 20 states for latency calculations). The
calculations add fixed and variable interrupt times (See Table 4.12. ) to this instruction time to predict latency. The
worst-case latency (both fixed and variable times included) is expressed by a pseudo-formula :
4.16
Notes:
1. <64K/>64K means inside/outside the 64-Kbyte memory region where code is executing.
2. Base-case fixed time is 16 states and assumes :
Number of
Variable
Added
States
– a 2-byte instruction is the first ISR byte
– Internal execution
– <64K jump to ISR
– Internal stack
– Internal peripheral interrupt
FIXED_TIME + VARIABLES + LONGEST_INSTRUCTION = MAXIMUM LATENCY PREDICTION
INT0#
INT1#
T2EX
1
Sample INT0#
Instruction
Execution
External
10–State
Request
INT0#
2
Time
State
OSC
Table 4.12. Interrupt Latency Variables
Figure 4.6. Response Time Example
Mode
Page
1
Response Time = 4
Jump to
ISR
>64
8
(1)
External
Memory
bus cycle
State
Wait
1 per
PUSH PC
External
<64K
Stack
4
(1)
External
>64K
Stack
Rev. C – May 7, 1999
8
(1)
External
bus cycle
Stack
State
Wait
1 per