TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 42

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. C – May 7, 1999
4.6.8. Latency Calculations
Assume the use of a zero-wait-state external memory where current instructions, the ISR and the stack are located
within the same 64-Kbyte memory region (compatible with memory maps for 80C51 microcontrollers.) Further,
assume there are 3 states yet to complete in the current 21-state DIV instruction when INT0# requests service. Also
assume INT0# has made the request one state prior to the sample state. Unlike in Figure 4.6. , the response time for
this assumption is three state times as the current instruction completes in time for the branch to occur. Latency
calculations begin with the minimum fixed latency of 16 states. From Table 4.12. , one state is added for an INT0#
request from external hardware; two states are added for external execution; and four states for an external stack in
the current 64-Kbyte region. Finally, three states are added for the current instruction to complete. The actual latency
is 26 states. Worst-case latency calculations predict 43 states for this example due to inclusion of total DIV instruction
time (less one state).
4.6.9. Blocking Conditions
If all enable and priority requirements have been met, a single prioritized interrupt request at a time generates a vector
cycle to an interrupt service routine. There are three causes of blocking conditions with hardware-generated vectors :
Any of these conditions blocks calls to interrupt service routines. Condition two ensures the instruction in progress
completes before the system vectors to the ISR. Condition three ensures at least one more instruction executes before
the system vectors to additional interrupts if the instruction in progress is a RETI or any write to IE0, IPH0 or IPL0.
The complete polling cycle is repeated each four state times.
An interrupt of equal or higher priority level is already in progress (defined as any point after the flag has been set
and the RETI of the ISR has not executed).
The current polling cycle is not the final cycle of the instruction in progress.
The instruction in progress is RETI or any write to the IE0, IPH0 or IPL0 registers.
Base Case Minimum Fixed Time
INT0# External Request
External Execution
<64K Byte Stack Location
Execution Time for Current (DIV instruction)
TOTAL
Table 4.13. Actual vs. Predicted Latency Calculations
Latency Factors
Actual
16
26
1
2
4
3
Predicted
TSC80251
16
20
43
1
2
4
4.17