TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 69

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
5.3. Instruction Set Summary
This section contains tables that summarize the instruction set. For each instruction there is a short description, its
length in bytes, and its execution time in states.
Notes:
5.3.1. Execution Times for Instructions that Access the Ports SFRs
The execution times for some instructions increases when the instruction accesses a Port SFR (Px, with x = 0-3) as
opposed to any other SFR. Table 5.34. lists these instructions and the execution times for Case 0 :
In cases 1 to 4, the instructions access a Port SFR :
The times for Cases 1 through 4 are expressed as the number of state times to add to the state times given for Case 0.
5.24
The instruction execution times given in the tables are for code executing from on-chip code memory and for
data that is read from and written to on-chip RAM. Execution times are increased by executing code from
external memory, accessing peripheral SFRs, accessing data in external memory, using wait states, or extending
the ALE pulse.
For some instructions, accessing the Port SFRs, Px, x = 0-3, increases the execution time. These cases are noted
individually in the tables.
Case 0: Code executes from on-chip ROM/OTPROM/EPROM and accesses locations in on-chip data RAM. The
Port SFRs are not accessed.
Case 1: Code executes from on-chip ROM/OTPROM/EPROM and accesses a Port SFR.
Case 2: Code executes from external memory with no wait state and a short ALE (not extended) and accesses a
Port SFR.
Case 3: Code executes from external memory with one wait state and a short ALE (not extended) and accesses a
Port SFR.
Case 4: Code executes from external memory with one wait state and an extended ALE, and accesses a Port SFR.
Rev. C – May 7, 1999