TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 20

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
3.4. TSC80251 Register File
The TSC80251 register file consists of 40 byte locations: 0-31 and 56-63, as shown in Figure 3.5. These locations are
accessible as bits, bytes, words and dwords. Several locations are dedicated to special registers; the others are
general–purpose registers.
Register file locations 0-7 actually consist of four switchable banks of eight registers each, as illustrated in
Figure 3.6. The four banks are implemented as the first 32 bytes of on–chip RAM and are always accessible as locations
00:0000h-00:001Fh in the memory address space. Only one of the four banks is accessible via the register file at a given
time. The accessible, or “active”, bank is selected by bits RS1 and RS0 in the PSW register, as shown in Table 3.2. This
bank selection can be used for fast context switches.
Register file locations 8-31 and 56-63 are always accessible. These locations are implemented as registers in the CPU.
Register file locations 32-55 are reserved and cannot be accessed.
3.4
Figure 3.3. Mappings C51 Architecture to C251 Architecture Address Spaces
FF:0000h
02:0000h
01:0000h
00:0000h
Bank 0
Bank 1
Bank 2
Bank 3
Bank
Bank
0000h
0000h
00h
External Data Memory
Internal Data Memory
Memory Address Space
C51 Architecture
C51 Architecture
C51 Architecture
Code Memory
16 Mbytes
Figure 3.4. TSC80251 Memory Space
00h-07h
08h-0Fh
10h-17h
18h-1Fh
Table 3.2. Register Bank Selection
Address Range
Address Range
FFFFh
FFFFh
FFh
S:100h
S:000h
08h
00h
80h
R0
C51 Architecture
RS1
C51 Architecture
Register File.
0
0
1
1
Register File
PSW Selection Bits
64 Bytes
SFR Space
512 Bytes
SFRs
FFh
R7
S:1FFh
S:07Fh
3Fh
RS0
0
1
0
1
Rev. C – May 7, 1999