TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 35

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
4.5. Bit Instructions
A bit instruction addresses a specific bit in a memory location or SFR. There are four categories of bit instructions:
4.5.1. Bit Addressing
The bits that can be individually addressed are in the on–chip RAM and the SFRs (See Table 4.7. ). The bit instructions
that are unique to the C251 Architecture can address a wider range of bits than the instructions from the C51
Architecture.
There are some differences in the way the instructions from the two Architectures address bits. In the C51 Architecture,
a bit (denoted by bit51) can be specified in terms of its location within a certain register, or it can be specified by a
bit address in the range 00h-7Fh. The C251 Architecture does not have bit addresses as such. A bit can be addressed
by name or by its location within a certain register, but not by a bit address.
Table 4.8. illustrates bit addressing in the two Architectures by using two sample bits:
Table 4.9. lists the addressing modes for bit insructions, and Table 5.26 summarizes the bit instructions. “bit” denotes
a bit that is addressed by a new instruction in the C251 Architecture, and “bit51” denotes a bit that is addressed by an
instruction in the C51 Architecture.
4.10
C251 Architecture
C51 Architecture
On-chip RAM
On-chip RAM
SFR
SFR
SETB (Set Bit), CLR (Clear Bit), CPL (Complement Bit). These instructions can set, clear or complement any
addressable bit.
ANL (And Logical), ANL/ (And Logical Complement), ORL (OR Logical), ORL/ (Or Logical Complement).
These instructions allow anding and oring of any addressable bit or its complement with the CY flag.
MOV (Move) instructions transfer any addressable bit to the carry (CY) bit or vice versa.
Bit–conditional jump instructions execute a jump if the bit has a specified state. The bit–conditional jump
instructions are classified with the control instructions.
RAMBIT is bit 5 in RAMREG, which is location 23h. (“RAMBIT” and “RAMREG” are assumed to be defined
in user code.)
IT1 is bit 2 in TCON, which is an SFR at location 88h.
Architecture
Architecture
Location
On-chip RAM
20h-7Fh
20h-2Fh
Register Name
Register Address
Bit Name
Bit Address
Register Name
Register Address
Bit Name
Bit Address
Table 4.8. Two Samples of Bits Addressing
Addressing Mode
Table 4.7. Bit-addressable Locations
All defined SFRs
SFRs with addresses ending in 0h or 8h: 80h, 88h, 90h, 98h, ..., F8h
Bit-addressable Locations
RAMREG.5
23h.5
RAMBIT
1Dh
TCON.2
88.2h
IT1
8A
C51 Architecture
SFRs
RAMREG.5
23h.5
RAMBIT
NA
TCON.2
S:88.2h
IT1
NA
C251 Architecture
Rev. C – May 7, 1999