TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 46

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. C – May 7, 1999
Instruction Set Reference
This chapter contains reference material for the instructions in the C251 Architecture. It includes an opcode map, a
summary of the instructions–with instruction lengths and execution times–and a detailed description of each
instruction. It contains the following tables:
Notes:
The instruction execution times given in this appendix are for code executing from on-chip code memory and for data that is read from and
written to on-chip RAM. Execution times are increased by executing code from external memory, accessing peripheral SFRs, accessing data in
external memory, using a wait state, or extending the ALE pulse.
For some instructions, accessing the Port SFRs, Px, x = 0-3, increases the execution time.
5.1. Instruction Set Summary
This section contains tables that summarize the instruction set. For each instruction there is a short description, its
length in bytes, and its execution time in states (one state time is equal to two system clock cycles). There are two con-
current processes limiting the effective instruction throughput:
Table 5.7. to Table 5.21. assume code executing from on–chip memory, then the CPU is fetching 16–bit at a time and
this is never limiting the execution speed.
If the code is fetched from external memory, a pre–fetch queue will store instructions ahead of execution to optimize
the memory bandwidth usage when slower instructions are executed. However, the effective speed may be limited de-
pending on the average size of instructions (for the considered section of the program flow). The maximum average
instruction throughput is provided by Table 5.1. depending on the external memory configuration (from Page Mode
to Non–Page Mode and the maximum number of wait states). If the average size of instructions is not an integer, the
maximum effective throughput is found by pondering the number of states for the neighbor integer values.
Table 5.1. through Table 5.4. describe the notation used for the instruction operands.
Table 5.6. and Table 5.7. comprise the opcode map for the instruction set.
Table 5.8. through Table 5.17. contain supporting material for the opcode map.
Table 5.18. lists execution times for a group of instructions that access the Port SFRs.
The following tables list the instructions with their lengths in bytes and their execution times:
Instruction Fetch
Instruction Execution
Add and Subtract Instructions, Table 5.7.
Increment and Decrement Instructions, Table 5.8.
Compare Instructions, Table 5.9.
Logical Instructions, Table 5.10. to Table 5.11.
Multiply, Divide and Decimal-adjust Instructions, Table 5.12.
Move Instructions, Table 5.13. to Table 5.15.
Bit Instructions, Table 5.16.
Exchange, Push and Pop Instructions, Table 5.17.
Control Instructions, Table 5.29.
TSC80251
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