TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 218

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
clear
code memory
configuration bytes
dir8
dir16
DPTR
DPX
deassert
double word
dword
EPROM
external address
integer
internal address
interrupt handler
interrupt latency
interrupt response time
interrupt service routine
LSB
MSB
glossary.2
The term clear refers to the value of a bit or the act of giving it a value. If a bit is
clear, its value is “0”; clearing a bit gives it a “0” value.
See program memory.
Bytes that determine a set of operating parameters for the TSC80251 Product. For
TSC80251 EPROM and OTPROM versions, these bytes are programmable in an
EPROM area. For TSC83251 masked ROM versions, these bytes are additional
information provided in a masked ROM area. For TSC80251 ROMless version,
these bytes are configured in factory according to the part number.
An 8–bit direct address. This can be a memory address or an SFR address.
A 16–bit memory address (00:0000h-00:FFFFh) used in direct addressing.
The 16–bit data pointer. In TSC80251 microcontrollers, DPTR is the lower 16 bits
of the 24–bit extended data pointer, DPX.
The 24–bit extended data pointer in TSC80251 microcontrollers. See also DPTR.
The term deassert refers to the act of making a signal inactive (disabled). The
polarity (high/low) is defined by the signal name. Active–low signals are
designated by a pound symbol (#) suffix; active–high signals have no suffix. To
deassert RD# is to drive it high; to deassert ALE is to drive it low.
A 32–bit unit of data. In memory, a double word comprises four contiguous bytes.
See double word.
Erasable programmable read–only memory.
A 16–bit or 17–bit address presented on the device pins. The address decoded by
an external device depends on how many of these address bits the external system
uses. See also internal address.
Any member of the set consisting of the positive and negative whole numbers and
zero.
The 24–bit address that the device generates. See also external address.
The module responsible for handling interrupts that are to be serviced by
user–written interrupt service routines.
The delay between an interrupt request and the time when the first instruction in
the interrupt service routine begins execution.
The time delay between an interrupt request and the resulting break in the current
instruction stream.
The software routine that services an interrupt.
Least–significant bit of a byte or a least–significant byte of a word.
Most–significant bit of a byte or a most–significant byte of a word.
Rev. C – May 7, 1999