TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 51

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
Notes:
1.
2.
3.
4.
5.
6.
5.6
Logical AND
Logical OR
Logical Exclusive OR
Clear
Complement
Rotate Left
Rotate Left Carry
Rotate Right
Rotate Right Carry
ANL
ANL
ORL
ORL
XRL
CLR
CPL
RL
RLC
RR
RRC
Mnemonic
Mnemonic
Logical instructions that affect a bit are in Table 5.16. .
A shaded cell denotes an instruction in the C51 Architecture.
If this instruction addresses an I/O Port (Px, x= 0–3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
If this instruction addresses an I/O Port (Px, x= 0–3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
(1)
(1)
(1)
(1)
A, Rn
A, dir8
A, @Ri
A, #data
dir8, A
dir8, #data
Rmd, Rms
WRjd, WRjs
Rm, #data
WRj, #data16
Rm, dir8
WRj, dir8
Rm, dir16
WRj, dir16
Rm, @WRj
Rm, @DRk
A
A
A
A
A
A
<src>
<dest>,
<dest>,
(1)
(2)
Table 5.10. Summary of Logical Instructions (1/2)
ANL <dest>, <src>
ORL <dest>, <src>
XRL <dest>, <src>
CLR A
CPL A
RL A
RLC A
RR A
RRC A
register to ACC
Direct address (on–chip RAM or SFR) to
ACC
Indirect address to ACC
Immediate data to ACC
ACC to direct address
Immediate 8–bit data to direct address
Byte register to byte register
Word register to word register
Immediate 8-bit data to byte register
Immediate 16-bit data to word register
Direct address to byte register
Direct address to word register
Direct address (64K) to byte register
Direct address (64K) to word register
Indirect address (64K) to byte register
Indirect address (16M) to byte register
Clear ACC
Complement ACC
Rotate ACC left
Rotate ACC left through CY
Rotate ACC right
Rotate ACC right through CY
Comments
Comments
dest opnd
dest opnd
dest opnd
(A)
(A)
(A)
(A)
(A)
(CY)
(A)
(A)
(A)
(A)
(CY)
(A)
n+1
0
n+1
0
n–1
7
n–1
7
0
(A)
(CY)
(A)
(CY)
(A)
(A)
Bytes
(A)
(A)
(A)
Binary Mode
(A)
(A)
7
0
1
2
1
2
2
3
3
3
4
5
4
4
5
5
4
4
1
1
1
1
1
1
7
0
dest opnd
dest opnd V src opnd
dest opnd
n
n
n
n
, n= 7..1
, n= 7..1
, n= 0..6
, n= 0..6
States
1
2
3
3
3
4
3
4
1
2
1
2
3
3
4
4
1
1
1
1
1
1
(3)
(4)
(4)
(3)
(5)
(6)
(5)
(5)
Rev. C – May 7, 1999
src opnd
src opnd
Bytes
Source Mode
2
2
2
2
2
3
2
2
3
4
3
3
4
4
3
3
1
1
1
1
1
1
States
1
2
3
2
2
3
2
3
2
3
1
1
2
2
3
3
1
1
1
1
1
1
(3)
(4)
(4)
(3)
(5)
(6)
(5)
(5)