TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 29

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
Instructions in the C51 Architecture use 80h-FFh as addresses for both memory locations and SFRs, because memory
locations are addressed only indirectly and SFR locations are addressed only directly. For compatibility, software tools
for TSC80251 controllers recognize this notation for instructions in the C51 Architecture. No change is necessary in
any code written for 80C51 microcontrollers.
For new instructions in the C251 Architecture, the memory region prefixes (00:, 01:, ..., FF:) and the SFR prefix (S:)
are required. Also, software tools for the C251 Architecture permit 00: to be used for memory addresses 00h-FFh and
permit the prefix S: to be used for SFR addresses in instructions in the C51 Architecture.
4.2.4. Addressing Modes
The C251 Architecture supports the following addressing modes:
4.3. Program Status Words
The Program Status Word (PSW) register and the Program Status Word 1 (PSW1) register contain four types of bits
(See Figure 4.7. and Figure 4.8. ):
The PSW and PSW1 registers are read/write registers; however, the parity bit in the PSW is not affected by a write.
Individual bits can be addressed with the bit instructions (“Bit Instructions”). The PSW and PSW1 bits are used
implicitly in the conditional jump instructions (“Conditional Jumps”).
4.4
Register Type
Register addressing
The instruction specifies the register that contains the operand.
Immediate addressing
The instruction contains the operand.
Direct addressing
The instruction contains the operand address.
Indirect addressing
The instruction specifies the register that contains the operand address.
Displacement addressing
The instruction specifies a register and an offset. The operand address is the sum of the register contents (the base
address) and the offset.
Relative addressing
The instruction contains the signed offset from the next instruction to the target address (the address for transfer
of control, e.g., the jump address).
Bit addressing
The instruction contains the bit address.
CY, AC, OV, N and Z are flags set by hardware to indicate the result of an operation.
The P bit indicates the parity of the accumulator.
Bits RS0 and RS1 are programmed by software to select the active register bank for registers R0-R7.
F0 and UD are available to the user as general–purpose flags.
Dword
Word
Byte
Byte
Table 4.3. Notation for Byte Registers, Word Registers, and Dword Registers
Register
Symbol
WRj
DRk
Rm
Rn
Ri
Destination
Register
WRjd
DRkd
Rmd
–
–
Register
Source
WRjs
DRks
Rms
–
–
R0, R1
R0-R7
R0-R15
WR0, WR2, WR4, ..., WR30
DR0, DR4, DR8, ..., DR28,DR56, DR60
Register Range
Rev. C – May 7, 1999