PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 93
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PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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TABLE 6-4:
2011 Microchip Technology Inc.
SSP2CON2
CMSTAT
PMADDRH/
PMDOUT1H
PMADDRL/
PMDOUT1L
PMDIN1H
PMDIN1L
TXADDRL
TXADDRH
RXADDRL
RXADDRH
DMABCL
DMABCH
UCON
USTAT
UEIR
UIR
UFRMH
UFRML
PMCONH
PMCONL
PMMODEH
PMMODEL
PMDOUT2H
PMDOUT2L
PMDIN2H
PMDIN2L
PMEH
PMEL
PMSTATH
PMSTATL
CVRCON
TCLKCON
DSGPR1
DSGPR0
DSCONH
DSCONL
DSWAKEH
DSWAKEL
Legend:
Note
File Name
(5)
(5)
1:
2:
3:
4:
5:
6:
7:
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5,6)
(5,6)
(5)
(5)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking Modes”
These bits and/or registers are only available on 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See
The TRISA6 and TRISA7 bits are only implemented when the pins are not configured for primary oscillator functions.
Parallel Port Out Data High Byte (Buffer 1)
Parallel Master Port Address Low Byte
Parallel Port Out Data Low Byte (Buffer 0)
Parallel Port In Data High Byte (Buffer 1)
Parallel Port In Data Low Byte (Buffer 0)
SPI DMA Transit Data Pointer Low Byte
SPI DMA Receive Data Pointer Low Byte
SPI DMA Byte Count Low Byte
Parallel Port Out Data High Byte (Buffer 3)
Parallel Port Out Data Low Byte (Buffer 2)
Parallel Port In Data High Byte (Buffer 3)
Parallel Port In Data Low Byte (Buffer 2)
Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep)
Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep)
WAITB1
PTEN15
PMPEN
CVREN
BTSEF
PTEN7
GCEN
GCEN
DSFLT
FRM7
BUSY
DSEN
CSF1
Bit 7
OBE
IBF
—
—
—
—
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED)
ACKSTAT
ACKSTAT
PPBRST
PTEN14
WAITB0
CVROE
for details.
ENDP3
PTEN6
IRQM1
SOFIF
FRM6
OBUF
CSF0
IBOV
Bit 6
CS1
—
—
—
—
—
—
—
—
—
—
—
—
Parallel Master Port Address High Byte
ADMSK5
STALLIF
WAITM3
PTEN13
ACKDT
ENDP2
DSULP
IRQM0
PTEN5
CVRR
FRM5
Bit 5
SE0
ALP
—
—
—
—
—
—
—
—
—
—
—
—
—
(4)
ADMSK4
ADRMUX1
WAITM2
PTEN12
PKTDIS
DSWDT
ACKEN
ENDP1
BTOEF
T1RUN
IDLEIF
INCM1
PTEN4
FRM4
Bit 4
—
—
—
—
—
—
—
—
—
—
—
r
(4)
SPI DMA Transit Data Pointer High Byte
SPI DMA Receive Data Pointer High Byte
ADMSK3
ADRMUX0
DFN8EF
WAITM1
PTEN11
USBEN
DSRTC
ENDP0
INCM0
PTEN3
TRNIF
RCEN
FRM3
CS1P
OB3E
CVR3
Bit 3
IB3F
—
—
—
—
—
—
—
PIC18F46J50 FAMILY
(4)
Section 11.1.2 “Data Registers”
ADMSK2
CRC16EF
ULPWDIS
RESUME
DSMCLR
PTBEEN
MODE16
WAITM0
PTEN10
ACTVIF
FRM10
PTEN2
FRM2
OB2E
CVR2
Bit 2
PEN
IB2F
BEP
DIR
—
—
—
—
r
(4)
2
SPI DMA Byte Count High
Byte
C™ Slave mode. See
ADMSK1
DSULPEN
PTWREN
SUSPND
CRC5EF
UERRIF
T3CCP2
MODE1
WAITE1
DSBOR
COUT2
PTEN9
PTEN1
WRSP
RSEN
FRM9
FRM1
OB1E
CVR1
Bit 1
PPBI
IB1F
—
—
(4)
RTCWDIS 0--- -000
RELEASE ---- -000
for more information.
PTRDEN
T3CCP1
URSTIF
MODE0
WAITE0
DSINT0
DSPOR
COUT1
PTEN8
PTEN0
PIDEF
FRM8
FRM0
RDSP
OB0E
CVR0
Bit 0
SEN
SEN
IB0F
—
—
Section 19.5.3.2 “Address
DS39931D-page 93
0000 0000 73, 270,
---- --11 73,
-000 0000 73,
0000 0000 73,
0000 0000 73,
0000 0000 73,
0000 0000 73,
0000 0000 73,
xxxx xxxx 73,
---- xxxx 73,
xxxx xxxx 73,
---- xxxx 73,
xxxx xxxx 73,
---- --xx 73,
-0x0 000- 73,
-xxx xxx- 73,
0--0 0000 73,
-000 0000 73,
---- -xxx 73,
xxxx xxxx 73,
0--0 0000 73,
000- 0000 73,
0000 0000 74,
0000 0000 74,
0000 0000 74,
0000 0000 74,
0000 0000 74,
0000 0000 74,
0000 0000 74,
0000 0000 74,
00-- 0000 74,
10-- 1111 74,
0000 0000 74,
---0 --00
uuuu uuuu
uuuu uuuu
---- ---0
0-00 00-1
POR, BOR
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