PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 181
PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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11.2.5
In the Addressable Parallel Slave Port mode
(
two extra inputs, PMA<1:0>, which are the Address
Lines 1 and 0. This makes the 4-byte buffer space
directly addressable as fixed pairs of read and write
buffers. As with Legacy Buffered mode, data is output
from PMDOUT1L, PMDOUT1H, PMDOUT2L and
PMDOUT2H, and is read in PMDIN1L, PMDIN1H,
PMDIN2L and PMDIN2H.
buffer addressing for the incoming address to the input
and output registers.
FIGURE 11-6:
11.2.5.1
When chip select is active and a read strobe occurs
(PMCS = 1 and PMRD = 1), the data from one of the
four output bytes is presented onto PMD<7:0>. Which
byte is read depends on the 2-bit address placed on
ADDR<1:0>.
FIGURE 11-7:
2011 Microchip Technology Inc.
PMMODEH<1:0> = 01), the module is configured with
PMD<7:0>
PMA<1:0>
PIC18F Master
PMWR
PMPIF
PMD<7:0>
PMA<1:0>
PMRD
PMCS
OBE
ADDRESSABLE PARALLEL SLAVE
PORT MODE
PMWR
PMRD
PMCS
READ FROM SLAVE PORT
Table 11-1
Address Bus
Data Bus
Control Lines
PARALLEL MASTER/SLAVE CONNECTION ADDRESSED BUFFER EXAMPLE
PARALLEL SLAVE PORT READ WAVEFORMS
provides the corresponding
Table 11-1
provides the
PMD<7:0>
PMA<1:0>
PMCS
PMRD
PMWR
PIC18F46J50 FAMILY
TABLE 11-1:
output registers and their associated address. When an
output buffer is read, the corresponding OBxE bit is set.
The OBxE flag bit is set when all the buffers are empty.
If any buffer is already empty, OBxE = 1, the next read
to that buffer will generate an OBUF event.
Address
Decode
Write
PMA<1:0>
00
01
10
11
PMDOUT1L (0)
PMDOUT1H (1)
PMDOUT2H (3)
PMDOUT2L (2)
PIC18F Slave
|
Q4
SLAVE MODE BUFFER
ADDRESSING
PMDOUT2H((3)
PMDOUT1H (1)
PMDOUT1L (0)
PMDOUT2L (2)
|
Register
Q1
(Buffer)
Output
Address
Decode
Read
|
Q2
PMDIN1H (1)
PMDIN2H (3)
PMDIN1L (0)
PMDIN2L (2)
|
DS39931D-page 181
Q3
Input Register
PMDIN1H (1)
PMDIN2H (3)
PMDIN1L (0)
PMDIN2L (2)
(Buffer)
|
Q4
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