PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 49
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PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
FIGURE 4-1:
FIGURE 4-2:
2011 Microchip Technology Inc.
Peripheral
Program
Counter
T1OSI
OSC1
Note 1: T
Clock
Clock
CPU Clock
CPU
PLL Clock
Peripheral
Program
Counter
Output
T1OSI
OSC1
Clock
Q1
SCS<1:0> Bits Changed
OST
Q2
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
PC
= 1024 T
Q3
Q4
Q1
OSC
Q1
T
; T
OST
1
PLL
(1)
PC
Q2
= 2 ms (approx). These intervals are not shown to scale.
2
Clock Transition
T
3
PLL (1)
OSTS Bit Set
Q3
Q4
PC + 2
n-1
PIC18F46J50 FAMILY
Figure
T1RUN bit is cleared, the OSTS bit is set and the
primary clock would be providing the clock. The IDLEN
and SCS bits are not affected by the wake-up; the
Timer1 oscillator continues to run.
Q1
1
n
Transition
2
Clock
4-2). When the clock switch is complete, the
n-1 n
Q2
PC + 2
Q3
Q2
Q4
Q3 Q4
Q1
Q1
PC + 4
Q2
Q2
PC + 4
DS39931D-page 49
Q3
Q3
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