PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 310
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PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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PIC18F46J50 FAMILY
19.5.7.1
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I
different baud rates. This is done by using different
BRG reload values for each module.
FIGURE 19-19:
TABLE 19-3:
DS39931D-page 310
Note 1:
48 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
Baud Rate and Module
Interdependence
2
C interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE w/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
12 MHz
10 MHz
10 MHz
SCLx
4 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
F
2
C Master mode at
CY
SSPM<3:0>
Control
Reload
CLKO
24 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
CY
* 2
Reload
2
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
BRG Down Counter
C specification (which applies to rates greater than
SSPxADD<6:0>
BRG Value
0Ch
77h
18h
63h
03h
09h
27h
02h
09h
2011 Microchip Technology Inc.
F
OSC
/4
(2 Rollovers of BRG)
400 kHz
400 kHz
333 kHz
1 MHz
100 kHz
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)
(1)
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