PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 148

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
10.6
Depending on the particular PIC18F46J50 family
device selected, PORTE is implemented in two
different ways.
For 44-pin devices, PORTE is a 3-bit wide port. Three
pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/
AN7/PMCS) are individually configurable as inputs or
outputs. These pins have Schmitt Trigger input buffers.
When selected as analog inputs, these pins will read as
‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISE
bit (= 0) will make the corresponding PORTE pin an
output (i.e., put the contents of the output latch on the
selected pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
REGISTER 10-5:
DS39931D-page 148
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-3
bit 2-0
Note:
Note:
R/W-0
RDPU
PORTE, TRISE and LATE
Registers
PORTE is available only on 44-pin devices.
On a POR, RE<2:0> are configured as
analog inputs.
RDPU: PORTD Pull-up Enable bit
1 = PORTD pull-ups are enabled by individual TRIS values
0 = All PORTD pull-ups are disabled
REPU: PORTE Pull-up Enable bit
1 = PORTE pull-ups are enabled by individual TRIS values
0 = All PORTE pull-ups are disabled
Unimplemented: Read as ‘0’
RE<2:0>: PORTE Data Input bits
R/W-0
REPU
PORTE REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
EXAMPLE 10-6:
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by setting bit, REPU (PORTE<6>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
POR. The integrated weak pull-ups consist of a semi-
conductor structure similar to, but somewhat different,
from a discrete resistor. On an unloaded I/O pin, the
weak pull-ups are intended to provide logic high indica-
tion, but will not necessarily pull the pin all the way to
V
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB
U-0
CLRF
MOVLB
BSF
BSF
MOVLW
MOVWF
—
DD
levels.
LATE
0x0F
ANCON0,PCFG5 ;RE0/AN5 as digital
ANCON0,PCFG6 ;RE1/AN6 as digital
0x03
TRISE
R/W-0
RE2
INITIALIZING PORTE
 2011 Microchip Technology Inc.
;latch values
;ANCON registers not
;in access bank
;Example value used to
;initialize data direction
;RE0, RE1 as inputs
;RE2 as output
;Initialize LATE output
x = Bit is unknown
R/W-0
RE1
R/W-0
RE0
bit 0