PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 147

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 10-9:
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
 2011 Microchip Technology Inc.
PORTD
LATD
TRISD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1:
RD3/PMD3/
RP20
RD4/PMD4/
RP21
RD5/PMD5/
RP22
RD6/PMD6/
RP23
RD7/PMD7/
RP24
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I
Name
(1)
Pin
(1)
(1)
These registers are not available on 28-pin devices.
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TRISD7
LATD7
Bit 7
RD7
PORTD I/O SUMMARY (CONTINUED)
Function
PMD3
PMD4
PMD5
PMD6
PMD7
RP20
RP21
RP22
RP23
RP24
RD3
RD4
RD5
RD6
RD7
TRISD6
LATD6
Bit 6
RD6
Setting
TRIS
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
TRISD5
LATD5
Bit 5
RD5
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
TRISD4
LATD4
Bit 4
RD4
PORTD<3> data input.
LATD<3> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 20 input.
Remappable Peripheral Pin 20 output.
PORTD<4> data input.
LATD<4> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 21 input.
Remappable Peripheral Pin 21 output.
PORTD<5> data input.
LATD<5> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 22 input.
Remappable Peripheral Pin 22 output.
PORTD<6> data input.
LATD<6> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 23 input.
Remappable Peripheral Pin 23 output.
PORTD<7> data input.
LATD<7> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 24 input.
Remappable Peripheral Pin 24 output.
PIC18F46J50 FAMILY
TRISD3
LATD3
Bit 3
RD3
TRISD2
LATD2
Bit 2
RD2
Description
TRISD1
LATD1
Bit 1
RD1
2
C/SMB = I
TRISD0
LATD0
Bit 0
DS39931D-page 147
RD0
2
C/SMBus
on Page
Values
Reset
92
92
92