PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 219
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PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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15.5.4
When Timer3 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer3
Gate Single Pulse mode is first enabled by setting the
T3GSPM bit in the T3GCON register. Next, the
T3GGO/T3DONE bit in the T3GCON register must be
set.
The Timer3 will be fully enabled on the next increment-
ing edge. On the next trailing edge of the pulse, the
T3GGO/T3DONE bit will automatically be cleared. No
FIGURE 15-4:
2011 Microchip Technology Inc.
TMR3GIF
TMR3GE
T3GSPM
T3DONE
T3GPOL
T3GVAL
T3GGO/
T3G_IN
Timer3
T1CKI
TIMER3 GATE SINGLE PULSE
MODE
TIMER3 GATE SINGLE PULSE MODE
N
Cleared by Software
Counting Enabled on
Rising Edge of T3G
Set by Software
N + 1
PIC18F46J50 FAMILY
other gate events will be allowed to increment Timer3
until the T3GGO/T3DONE bit is once again set in
software.
Clearing the T3GSPM bit of the T3GCON register will
also clear the T3GGO/T3DONE bit. See
for timing details.
Enabling the Toggle mode and the Single Pulse mode,
simultaneously, will permit both sections to work
together. This allows the cycle times on the Timer3 gate
source to be measured. See
details.
Set by Hardware on
Falling Edge of T3GVAL
Cleared by Hardware on
Falling Edge of T3GVAL
N + 2
Figure 15-5
DS39931D-page 219
Cleared by
Software
Figure 15-4
for timing
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