PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 82

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
6.2
6.2.1
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the PC is incremented
on every Q1; the instruction is fetched from the pro-
gram memory and latched into the Instruction Register
(IR) during Q4. The instruction is decoded and exe-
cuted during the following Q1 through Q4.
illustrates the clocks and instruction execution flow.
FIGURE 6-4:
EXAMPLE 6-3:
DS39931D-page 82
1. MOVLW 55h
2. MOVWF LATB
3. BRA SUB_1
4. BSF
5. Instruction @ address SUB_1
Note:
OSC2/CLKO
(RC mode)
PIC18 Instruction Cycle
CLOCKING SCHEME
LATA, 3 (Forced NOP)
OSC1
All instructions are single-cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then exe-
cuted.
PC
Q1
Q2
Q3
Q4
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Execute INST (PC – 2)
Fetch INST (PC)
Q2
Fetch 1
T
PC
CY
Q3
0
Q4
Execute 1
Figure 6-4
Fetch 2
T
CY
1
Q1
Fetch INST (PC + 2)
Execute INST (PC)
Q2
Execute 2
Fetch 3
PC + 2
T
CY
2
6.2.2
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the PC to change (e.g., GOTO), then
two cycles are required to complete the instruction
(Example
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the IR in the Q1 cycle. This instruction is then
decoded and executed during the Q2, Q3 and Q4
cycles. Data memory is read during Q2 (operand read)
and written during Q4 (destination write).
Q3
Q4
Execute 3
Fetch 4
T
6-3).
CY
INSTRUCTION FLOW/PIPELINING
3
Q1
Execute INST (PC + 2)
Fetch INST (PC + 4)
Fetch SUB_1 Execute SUB_1
Flush (NOP)
Q2
PC + 4
T
 2011 Microchip Technology Inc.
CY
4
Q3
Q4
T
CY
Internal
Phase
Clock
5