PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 338

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
TABLE 20-6:
20.2.3
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the BRG is inactive and a
proper byte reception cannot be performed. The
auto-wake-up feature allows the controller to wake-up
due to activity on the RXx/DTx line while the EUSART
is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the
LIN/J2602 support protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure
Sleep mode
cleared by reading the RCREGx register.
The WUE bit is automatically cleared once a
low-to-high transition is observed on the RXx line
following the wake-up event. At this point, the EUSART
module is in Idle mode and returns to normal operation.
This signals to the user that the Sync Break event is
over.
DS39931D-page 338
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
20-8) and asynchronously if the device is in
These bits are only available on 44-pin devices.
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
(Figure
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
PMPIE
PMPIP
PMPIF
SSP2IF
SSP2IE
SSP2IP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
20-9). The interrupt condition is
(1)
(1)
(1)
BCL2IE
BCL2IP
BCL2IF
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
RXDTP
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
TXEN
Bit 5
TXCKP
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
SYNC
Bit 4
TMR4IE
TMR4IP
TMR4IF
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
BRG16
20.2.3.1
Since auto-wake-up functions by sensing rising edge
transitions on RXx/DTx, information with any state
changes before the Stop bit may signal a false
End-of-Character (EOC) and cause data or framing
errors. To work properly, therefore, the initial character
in the transmission must be all ‘0’s. This can be 00h
(8 bits) for standard RS-232 devices or 000h (12 bits)
for LIN/J2602 bus.
Oscillator start-up time must also be considered,
especially in applications using oscillators with
longer start-up intervals (i.e., HS or HSPLL mode).
The Sync Break (or Wake-up Signal) character must
be of sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected
oscillator to start and provide proper initialization of
the EUSART.
RBIE
Bit 3
CTMUIE TMR3GIE
CTMUIP TMR3GIP
CTMUIF TMR3GIF
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
Special Considerations Using
Auto-Wake-up
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
 2011 Microchip Technology Inc.
TMR1IF
TMR1IE
TMR1IP
RTCCIE
RTCCIP
RTCCIF
ABDEN
RX9D
TX9D
RBIF
Bit 0
on Page:
Values
Reset
69
72
72
72
72
72
72
71
71
71
73
71
71