PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 550

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J50 FAMILY
Flash Program Memory .................................................... 103
FSCM. See Fail-Safe Clock Monitor.
G
Getting Started Guidelines ........................................... 29, 30
GOTO ............................................................................... 456
H
Hardware Multiplier .......................................................... 113
High/Low-Voltage Detect ................................................. 395
I
I/O Ports ........................................................................... 131
I
I
DS39931D-page 550
2
2
C Mode .......................................................................... 288
C Mode (MSSP)
Associated Registers ............................................... 112
Control Registers ..................................................... 104
Erase Sequence ...................................................... 108
Erasing ..................................................................... 108
Memory Write Sequence ......................................... 111
Operation During Code-Protect ............................... 112
Reading .................................................................... 107
Table Pointer
Table Pointer Boundaries ........................................ 106
Table Reads and Table Writes ................................ 103
Write Sequence ....................................................... 109
Writing ...................................................................... 109
Connection Requirements ......................................... 29
External Oscillator Pins .............................................. 33
ICSP Pins ................................................................... 32
Power Supply Pins ..................................................... 30
Unused I/Os ............................................................... 33
Voltage Regulator Pins (V
8 x 8 Multiplication Algorithms ................................. 113
Operation ................................................................. 113
Performance Comparison (table) ............................. 113
Applications .............................................................. 399
Associated Registers ............................................... 400
Characteristics ......................................................... 507
Current Consumption ............................................... 397
Effects of a Reset ..................................................... 400
Operation ................................................................. 396
Setup ........................................................................ 397
Start-up Time ........................................................... 397
Typical Application ................................................... 399
Open-Drain Outputs ................................................. 133
Pin Capabilities ........................................................ 132
TTL Input Buffer Option ........................................... 133
Acknowledge Sequence Timing ............................... 316
Associated Registers ............................................... 322
Baud Rate Generator ............................................... 309
Bus Collision
Clock Arbitration ....................................................... 311
EECON1 and EECON2 ................................... 104
TABLAT (Table Latch) Register ....................... 106
TBLPTR (Table Pointer) Register .................... 106
Boundaries Based on Operation ...................... 106
Unexpected Termination .................................. 112
Write Verify ...................................................... 112
During Sleep .................................................... 400
During a Repeated Start Condition .................. 320
During a Stop Condition ................................... 321
CAP
/V
DDCORE
) ................... 31
INCF ................................................................................ 456
INCFSZ ............................................................................ 457
In-Circuit Debugger .......................................................... 434
In-Circuit Serial Programming (ICSP) ...................... 417, 434
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 482
Indirect Addressing ............................................................ 98
INFSNZ ............................................................................ 457
Initialization Conditions for All Registers ...................... 69–76
Instruction Cycle ................................................................ 82
Instruction Set .................................................................. 435
Clock Stretching ....................................................... 303
Clock Synchronization and CKP bit ......................... 304
Effects of a Reset .................................................... 317
General Call Address Support ................................. 307
I
Master Mode ............................................................ 308
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 317
Operation ................................................................. 293
Read/Write Bit Information (R/W Bit) ............... 293, 296
Registers ................................................................. 288
Serial Clock (SCLx Pin) ........................................... 296
Slave Mode .............................................................. 293
Sleep Operation ....................................................... 317
Stop Condition Timing ............................................. 316
and Standard PIC18 Instructions ............................. 482
Clocking Scheme ....................................................... 82
Flow/Pipelining ........................................................... 82
ADDLW .................................................................... 441
ADDWF .................................................................... 441
ADDWF (Indexed Literal Offset Mode) .................... 483
ADDWFC ................................................................. 442
ANDLW .................................................................... 442
ANDWF .................................................................... 443
BC ............................................................................ 443
BCF ......................................................................... 444
BN ............................................................................ 444
BNC ......................................................................... 445
BNN ......................................................................... 445
BNOV ...................................................................... 446
BNZ ......................................................................... 446
BOV ......................................................................... 449
BRA ......................................................................... 447
BSF .......................................................................... 447
BSF (Indexed Literal Offset Mode) .......................... 483
BTFSC ..................................................................... 448
BTFSS ..................................................................... 448
BTG ......................................................................... 449
2
C Clock Rate w/BRG ............................................. 310
10-Bit Slave Receive Mode (SEN = 1) ............ 303
10-Bit Slave Transmit Mode ............................ 303
7-Bit Slave Receive Mode (SEN = 1) .............. 303
7-Bit Slave Transmit Mode .............................. 303
Operation ......................................................... 309
Reception ........................................................ 313
Repeated Start Condition Timing .................... 312
Start Condition Timing ..................................... 311
Transmission ................................................... 313
and Arbitration ................................................. 317
Addressing ....................................................... 293
Addressing Masking Modes
Reception ........................................................ 296
Transmission ................................................... 296
5-Bit ......................................................... 294
7-Bit ......................................................... 295
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