MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 54

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. x16: A9 and A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
A0-A9, A11
BA0, BA1
DQM /
CKE
2.
3. Page left open; no
CLK
A10
DQ
t
WR must be satisfied prior to PRECHARGE command.
x8: A11 = “Don’t Care”
MIN
0.8
1.5
2.5
2.5
7.5
0.8
t CMS
t CKS
7
t AS
t AS
t AS
-7E
ACTIVE
BANK
T0
ROW
ROW
MAX
t CKH
t CMH
t AH
t AH
t AH
t RCD
MIN
t CL
0.8
1.5
2.5
2.5
7.5
0.8
10
t
RP.
T1
-75
NOP
t CH
MAX
t CMS
t CK
MIN
t DS
COLUMN m 1
10
1
2
3
3
8
1
D
T2
WRITE
BANK
WRITE – FULL-PAGE BURST
IN
-8E
t CMH
m
t DH
MAX
t DS
UNITS
D
ns
ns
ns
ns
ns
ns
ns
IN
T3
NOP
m + 1
t DH
54
1,024 (x8) locations within same row
2,048 (x4) locations within same row
512 (x16) locations within same row
t DS
SYMBOL*
D
t
t
t
t
t
t
CKS
CMH
CMS
DH
DS
RCD
IN
T4
NOP
m + 2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
Full page completed
MIN
1.5
0.8
1.5
0.8
1.5
15
t DS
D
IN
T5
-7E
NOP
m + 3
MAX
t DH
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
(
(
128Mb: x4, x8, x16
(
)
(
(
(
(
(
(
)
(
)
)
(
)
(
)
(
)
(
)
(
)
)
)
(
)
)
)
)
)
(
(
)
(
)
)
(
)
(
)
)
MIN
t DS
1.5
0.8
1.5
0.8
1.5
20
D
Tn + 1
IN
NOP
-75
m - 1
t DH
MAX
Full-page burst does not
self-terminate. Can use
BURST TERMINATE
command to stop.
MIN
BURST TERM
20
Tn + 2
2
1
2
1
2
©2001, Micron Technology, Inc.
SDRAM
-8E
MAX
DON’T CARE
2, 3
UNITS
Tn + 3
NOP
ns
ns
ns
ns
ns
ns