MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 27

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out appear-
ing CAS latency later. The PRECHARGE to bank n will
begin after
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
t
WR is met, where
Internal
States
Internal
States
NOTE: 1. DQM is LOW.
NOTE: 1. DQM is LOW.
WRITE With Auto Precharge Interrupted by a WRITE
WRITE With Auto Precharge Interrupted by a READ
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
CLK
CLK
DQ
DQ
t
WR begins when the
Page Active
Page Active
T0
NOP
T0
NOP
WRITE - AP
WRITE - AP
BANK n,
BANK n,
Page Active
Page Active
BANK n
BANK n
COL a
COL a
T1
D
T1
D
a
a
IN
IN
WRITE with Burst of 4
WRITE with Burst of 4
Figure 27
Figure 26
a + 1
T2
a + 1
T2
D
D
NOP
NOP
IN
IN
27
BANK m,
READ - AP
a + 2
T3
COL d
T3
D
BANK m
NOP
IN
4. Interrupted by a WRITE (with or without auto
Interrupt Burst, Write-Back
t
CAS Latency = 3 (BANK m)
WR - BANK n
READ with Burst of 4
precharge): A WRITE to bank m will interrupt a WRITE
on bank n when registered. The PRECHARGE to bank
n will begin after
the
The last valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m
(Figure 27).
BANK m,
WRITE - AP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COL d
BANK m
T4
T4
D
NOP
d
t
IN
Interrupt Burst, Write-Back
WR - BANK n
WRITE with Burst of 4
WRITE
T5
T5
d + 1
NOP
NOP
D
IN
Precharge
t
RP - BANK n
t
to
WR is met, where
128Mb: x4, x8, x16
T6
T6
d + 2
D
NOP
NOP
D
OUT
d
t RP - BANK n
IN
Precharge
bank
DON’T CARE
T7
T7
d + 3
D
d + 1
NOP
NOP
D
t WR - BANK m
t RP - BANK m
OUT
IN
Write-Back
m
t
is
©2001, Micron Technology, Inc.
WR begins when
SDRAM
registered.