MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 49

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
DQML, DQMH
COMMAND
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
A0-A9, A11
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
BA0, BA1
DQM /
CKE
CLK
A10
DQ
2. 15ns is required between <D
3. x16: A9 and A11 = “Don’t Care”
t CMS
t CKS
x8: A11 = “Don’t Care”
t AS
t AS
t AS
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
7
ACTIVE
T0
ROW
ROW
BANK
-7E
t CKH
t CMH
t AH
t AH
t AH
MAX
t RCD
t RAS
t RC
t CK
T1
NOP
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
10
-75
DISABLE AUTO PRECHARGE
MAX
t CMS
t CL
t DS
COLUMN m 3
WRITE – WITHOUT AUTO PRECHARGE
WRITE
T2
BANK
D
IN
t CMH
IN
t CH
t DH
m
MIN
m + 3> and the PRECHARGE command, regardless of frequency.
10
1
2
3
3
8
1
2
1
-8E
t DS
MAX
D
IN
T3
NOP
m + 1
t DH
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t DS
D
IN
T4
NOP
m + 2
49
t DH
t DS
SYMBOL* MIN
t
t
t
t
t
t
t
t
CMS
DH
DS
RAS
RC
RCD
RP
WR
D
IN
NOP
T5
m + 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
1.5
0.8
1.5
37
60
15
15
14
t WR
NOP
T6
-7E
2
120,000
MAX
SINGLE BANK
128Mb: x4, x8, x16
PRECHARGE
1
ALL BANKS
BANK
T7
MIN
1.5
0.8
1.5
44
66
20
20
15
-75
120,000
MAX
t RP
NOP
T8
MIN
50
70
20
20
15
2
1
2
©2001, Micron Technology, Inc.
SDRAM
-8E
120,000
ACTIVE
MAX
ROW
ROW
BANK
T9
DON’T CARE
UNITS
ns
ns
ns
ns
ns
ns
ns
ns