MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 51

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
DQML, DQMH
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
COMMAND
A0-A9, A11
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
BA0, BA1
DQM /
CKE
A10
CLK
DQ
2. 15ns is required between <D
3. x16: A9 and A11 = “Don’t Care”
4. PRECHARGE command not allowed else
x8: A11 = “Don’t Care”
t CMS
t CKS
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
t AS
t AS
t AS
7
ACTIVE
T0
ROW
ROW
BANK
-7E
t CKH
t CMH
t AH
t AH
t AH
MAX
t RCD
t RAS
t RC
t CK
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
10
T1
NOP
SINGLE WRITE – WITHOUT AUTO PRECHARGE
-75
MAX
DISABLE AUTO PRECHARGE
t CMS
t CL
t DS
COLUMN m 3
IN
WRITE
BANK
T2
D
MIN
m> and the PRECHARGE command, regardless of frequency.
10
IN
1
2
3
3
8
1
2
1
t CMH
t CH
t DH
m
t WR
-8E
MAX
2
t
RAS would be violated.
NOP 4
T3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
51
NOP 4
T4
SYMBOL* MIN
t
t
t
t
t
t
t
t
CMS
DH
DS
RAS
RC
RCD
RP
WR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PRECHARGE
SINGLE BANK
ALL BANKS
T5
BANK
1.5
0.8
1.5
37
60
15
15
14
-7E
120,000
MAX
t RP
T6
NOP
128Mb: x4, x8, x16
MIN
1.5
0.8
1.5
44
66
20
20
15
1
-75
120,000
MAX
ACTIVE
BANK
ROW
T7
MIN
50
70
20
20
15
2
1
2
©2001, Micron Technology, Inc.
SDRAM
-8E
120,000
NOP
T8
DON’T CARE
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns