MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 15

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

Operation
BANK/ROW ACTIVATION
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE com-
mand, which selects both the bank and the row to be
activated (see Figure 3).
READ or WRITE command may be issued to that row,
subject to the
divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after
the ACTIVE command on which a READ or WRITE com-
mand can be entered. For example, a
of 20ns with a 125 MHz clock (8ns period) results in 2.5
clocks, rounded to 3. This is reflected in Figure 4, which
covers any case where 2 <
procedure is used to convert other specification limits
from time units to clock cycles.)
the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Before any READ or WRITE commands can be issued
After opening a row (issuing an ACTIVE command), a
A subsequent ACTIVE command to a different row in
A subsequent ACTIVE command to another bank can
t
RCD specification.
COMMAND
Example: Meeting
CLK
t
RCD (MIN)/
ACTIVE
T0
t
RCD (MIN) should be
t
RCD specification
t
t
CK ≤ 3. (The same
RC.
t
RRD.
t
RCD (MIN) When 2 <
NOP
T1
Figure 4
t
RCD
15
A0–A10, A11
BA0, BA1
T2
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Activating a Specific Row in a
RAS#
CAS#
WE#
CKE
CLK
CS#
t
RCD (MIN)/
HIGH
Specific Bank
READ or
WRITE
T3
128Mb: x4, x8, x16
Figure 3
DON’T CARE
t
CK < 3
ADDRESS
ADDRESS
BANK
ROW
T4
©2001, Micron Technology, Inc.
SDRAM