MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 44

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
DQML, DQMH
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
t
COMMAND
A0-A9, A11
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
BA0, BA1
DQM /
CKE
CLK
A10
DQ
2. x16: A9 and A11 = “Don’t Care”
3. PRECHARGE command not allowed or
PRECHARGE.
t CMS
x8: A11 = “Don’t Care”
t CKS
t AS
t AS
t AS
0.8
1.5
2.5
2.5
7.5
0.8
1.5
7
ACTIVE
ROW
ROW
BANK
T0
-7E
t CMH
t CKH
t AH
t AH
t AH
MAX
5.4
5.4
t RCD
t RAS
t RC
t CK
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
T1
NOP
SINGLE READ – WITHOUT AUTO PRECHARGE
-75
DISABLE AUTO PRECHARGE
MAX
5.4
6
t CMS
t CL
COLUMN m
BANK
T2
READ
MIN
10
t CMH
1
2
3
3
8
1
2
t CH
CAS Latency
-8E
2
MAX
t
6
6
RAS would be violated.
T3
NOP
t LZ
UNITS
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t AC
44
T4
D
NOP
OUT
t OH
t HZ
3
m
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
t
CMH
CMS
HZ(3)
HZ(2)
LZ
OH
RAS
RC
RCD
RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SINGLE BANKS
PRECHARGE
ALL BANKS
BANK(S)
T5
t RP
0.8
1.5
37
60
15
15
1
3
-7E
120,000
MAX
5.4
5.4
T6
NOP
128Mb: x4, x8, x16
MIN
0.8
1.5
44
66
20
20
1
3
1
-75
120,000
ACTIVE
ROW
MAX
ROW
BANK
T7
5.4
6
MIN
50
70
20
20
1
2
1
3
©2001, Micron Technology, Inc.
SDRAM
-8E
T8
120,000
NOP
MAX
6
6
DON’T CARE
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns