MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 39

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

DQML, DQMH
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
COMMAND
A0-A9, A11
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
DQM /
BA0, BA1
CKE
A10
CLK
DQ
2. x16: A9 and A11 = “Don’t Care”
t CMS
x8: A11 = “Don’t Care”
t CKS
t AS
t AS
t AS
COLUMN m
0.8
1.5
2.5
2.5
7.5
0.8
7
READ
T0
BANK
-7E
t CMH
t CKH
t AH
t AH
t AH
MAX
2
5.4
5.4
t CMS
t CK
T1
MIN
NOP
0.8
1.5
2.5
2.5
7.5
0.8
10
t CMH
-75
MAX
5.4
t CL
t CKS t CKH
6
T2
NOP
t LZ
t CH
MIN
10
t AC
1
2
3
3
8
1
-8E
CLOCK SUSPEND MODE
MAX
6
6
T3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
OUT
m
T4
NOP
39
t OH
t AC
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
CKS
CMH
CMS
DH
DS
HZ(3)
HZ(2)
LZ
OH
D
T5
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
m + 1
t HZ
1.5
0.8
1.5
0.8
1.5
1
3
1
-7E
T6
NOP
MAX
5.4
5.4
128Mb: x4, x8, x16
COLUMN e 2
t DS
MIN
1.5
0.8
1.5
0.8
1.5
BANK
D
1
3
WRITE
T7
OUT
t DH
e
-75
MAX
5.4
6
T8
MIN
2
1
2
1
2
1
3
©2001, Micron Technology, Inc.
SDRAM
-8E
MAX
6
6
D
DON’T CARE
UNDEFINED
OUT
T9
NOP
e + 1
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns