MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 38

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
SYMBOL* MIN
t
t
t
t
t
AH
AS
CH
CL
CK (3)
DQML, DQMH
COMMAND
A0-A9, A11
Precharge all
DQM /
BA0, BA1
active banks
CLK
CKE
A10
DQ
0.8
1.5
2.5
2.5
7
-7E
t CMS
High-Z
t CKS
t AS
SINGLE BANK
MAX
PRECHARGE
ALL BANKS
BANK(S)
T0
t CMH
t CKH
t AH
MIN
0.8
1.5
2.5
2.5
7.5
Two clock cycles
-75
All banks idle, enter
power-down mode
t CK
MAX
T1
NOP
MIN
1
2
3
3
8
-8E
t CKS
t CL
POWER-DOWN MODE
MAX
T2
NOP
Input buffers gated off while in
power-down mode
t CH
UNITS
ns
ns
ns
ns
ns
38
Exit power-down mode
SYMBOL* MIN
t
t
t
t
t
CK (2)
CKH
CKS
CMH
CMS
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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1
7.5
0.8
1.5
0.8
1.5
-7E
MAX
t CKS
128Mb: x4, x8, x16
Tn + 1
MIN
0.8
1.5
0.8
1.5
10
NOP
All banks idle
-75
MAX
MIN
Tn + 2
10
ACTIVE
1
2
1
2
©2001, Micron Technology, Inc.
ROW
ROW
BANK
SDRAM
-8E
DON’T CARE
MAX
UNITS
ns
ns
ns
ns
ns