MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 12

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

Commands
commands. This is followed by a written description of
each command. Three additional Truth Tables appear
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Note: 1)
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
Truth Table 1 provides a quick reference of available
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A9; A11 (x4); A0-A9 (x8); or A0-A8 (x16) provide column address; A10 HIGH enables the auto precharge feature
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read
from or written to.
Care.”
12
CS# RAS# CAS# WE# DQM
H
L
L
L
L
L
L
L
–
–
L
following the Operation section; these tables provide
current state/next state information.
X
H
H
H
H
–
–
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
X
H
H
L
L
L
L
–
–
X
H
H
H
H
L
L
L
L
–
–
128Mb: x4, x8, x16
L/H
L/H
X
X
X
X
X
X
X
H
L
8
8
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
–
–
©2001, Micron Technology, Inc.
High-Z
Active
Active
SDRAM
Valid
DQs
X
X
X
X
X
X
X
NOTES
6, 7
3
4
4
5
2
8
8